I've been researching 4th order CIC filters as well.   I found a really good article here where Richard Lyons explains CIC filters http://www.embedded.com/design/configurable-systems/4006446/Understanding-cascad...

He says Although recursive, happily CIC filters are guaranteed stable, linear-phase shown in Figure 4b, and have finite-length impulse responses.    So, even without reviewing your model, I suggest the only problem might be that round off errors in Mathcad introduced small errors in the location of the poles and zeros.  It seems intuitively reasonable to me that they must be stable given their time-series behavior.

Lyon's book, Understanding Digital Signal Processing, 2Ed, apparently contains more detailed description.   Personally, after reading his very clear article, I'm ready got go buy a copy of his book.

Now, I'm interested in implementing a 4th order CIC filter for decimating input from a PDM digital Microphone using a low-density FPGA.    Can anyone help express such a filter in Verilog, I'm a novice with this language?