Hi loose-electron,
Quote:One more time...
1) I need three clock edges. The first two form the sampling clock, and the last is to trigger an event.
2) 160 MHz. 40nm CMOS
3) alignment? Do you mean the spacing? The first two form a roughly 36% duty cycle (DC) clock. The last edge triggers just before the 36% DC clock.
4) Accuracy is not important (DC could be from 30% to 40% for example), but jitter should be around 1ps rms or less.
5) As this is a test chip, the clock source will be a signal generator.
you know, despite not giving
all of the information you asked for, I got some very useful answers. Raj. mentioned sensing the duty cycle, and RobG mentioned the use of dividers (although div 2 won't give the edges I need, div 3 or more might). I just need some general guidelines, and I'm intelligent enough to sort out what can and what can't be used in my system. Also, even if a method can't be used in my work, it may still be interesting to hear...
regards,
Aaron