Dear all,

I've no idea how to build EFT test modeling. EFT means that the high voltage pulse(+-4000 V, lasting for ~100 ns, 100kHz) is introduced to the input AC source and the system output should not go down to 0 V.What's more, the introduced pulse could affect every pin of the chip because of the small size of the whole system.
For now, it's very difficult to predict the performance on this issue without proper testbench. Now I'm looking forward to some advice from you. Thanks in advance.

Thank you very much for your help!
I'm wondering how to build such EFT pulses generator for simulation. I've no idea about the storage capacitor should be used.