Hi members,
We have a System clock running at 120MHz, it has 300pS peak to peak jitter.  :'(
I am designing a pipeline ADC and my sampling frequency is 1MHz.
I found that due to aperture uncertanity [jitter] my ADC's performance is limited.

Since my sampling frequency is much slower than my main noisy System clock, can I do somekind of filtering and create a new clean Clock?
what other methods can I use to improve jitter at low frequencies?

Thanks in advance.

Thanks for reply.

The system clock is a relaxation oscillator. I am not very familiar with clock design. But I guess relaxation oscillators are usually very noisy.
Is 300pS OK for relaxation oscillator? Is there some scope of improvement there?

"You can run a noisy clock into a PLL and get something out of the PLL that averages out the the mean value of the clock coming in, as a function of the PLL bandwidth."

Any prior publications which do this? Do I need a very accurate VCO to design this?  

Get rid of the relaxation oscillator and go to a crystal based oscillator.

Before you try anything else.

Using a crystal should fix your problems.