14 bit is pushing it for a pipelined ADC unless you want to calibrate or you don't really need 14-bit ENOB and your application is more SNDR oriented.  

That said, getting a 14-bit SAR to work well above 1 MS/s is non-trivial to say the least, but it depends on your process.

You really need to give more information for to make an informed choice.  What process are you using?  What are the key specs?  What is the signal bandwidth?  etc etc etc

Hi,


check out this work.

Kapusta, R. ; Analog Devices, Inc, et. Al., "A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS" JSSC vol. 48, no.12.

It seems that if you have a fast enough process, a SAR is doable. Also, if the design is doable using a SAR, then go with a SAR, but if the speed requirement can't be met, then pipeline. Perhaps the experts could weigh in on the pros and cons of pipeline versus SAR as I'm also very interested. My understanding:

FOR SAR
1) Only 1 linear node.
2) Lower power due to no high gain amplifiers.
3) More scalable and benefits more from technology scaling.
4) Easier to do with just one low-voltage supply.

FOR Pipelined
1) Faster.
2) In SAR, internal clock rate is N times higher than pipelined ADC.

Anybody care to add to that?


cheers,
Aaron

Hi,


Input voltage +/- 10V.

Is that a typo? What process are you using? What do you mean by 4:1 MUX?


Aaron

aaron_do wrote on Aug 5^th, 2014, 3:55am:



20V? Voltage division at the input with R-poly will get that done.

Foundry process is the big question here - if it is submicron CMOS at that sample rate I would go Sigma-Delta,

If it is old 1.2u CMOS SAR might be the path to take.

Very slow sampling rate so I do not see a need to do a pipeline.

i am really thankful for ua sugestions!!

i have to use AMS 180 nm Tech.

and it has to be designed for data acquisition system

OK, so 0.18, 14 bit, 4MHz sampling.

I would go through the literature and look at sigma delta, pipelines and SAR methods.

If power is a big issue the pipeline will eat a lot of power, sigma delta not as much.

Research papers next, If I may suggest.

I think the confusion is the OP hasn't ever said what the real specs are.  What is important?

Power?  Go with a SAR or pipelined-SAR like Rob suggests.

Time?  Go with a Pipelined ADC.  Maybe a 3.5-bit first stage and then 1.5-bit stages after that.  Since you're going slow, you don't have to worry about cap size and power.  Use the 3.3 V devices, make big, double-cascode op amps and don't worry too much.

OP doesn't seem to be an expert so going for something simple is the way to go.