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SAR and Pipelining Architectures (Read 13566 times)
SNIKE
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Re: SAR and Pipelining Architectures
Reply #15 - Aug 28th, 2014, 10:38pm
 
My 2 cents:

1) Delta sigma : Cannot be used. Because of 4 Inputs , we loose noise shaping [every time we reset, memory is lost] .
2)Pipeline ADC : Do you care about latency? If yes Pipeline is overkill.
use Cyclic or SAR instead.
3)Flash : Cannot be done. Need Fancy/expensive folding techniques.
4)Slope techniques: May be slow, requires huge oversampling. Good for multiplexing, as you can have separate registers and filters in digital domain. Again speed is issue.  

Historically SAR has been published with higher ENOB. I am inclined towards SAR.


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eternity
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Re: SAR and Pipelining Architectures
Reply #16 - Sep 2nd, 2014, 3:53am
 
Is the confusion regarding mentioned Vdd resolved?
10V for 180 nm process?
Highly unlikely as the oxide breakdown occurs way before you reach 10 V.

Eternity
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loose-electron
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Re: SAR and Pipelining Architectures
Reply #17 - Sep 3rd, 2014, 3:00pm
 
eternity wrote on Sep 2nd, 2014, 3:53am:
Is the confusion regarding mentioned Vdd resolved?
10V for 180 nm process?
Highly unlikely as the oxide breakdown occurs way before you reach 10 V.

Eternity


resistive voltage division before you hit a transistor
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Jerry Twomey
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