raja.cedt wrote on Aug 28th, 2014, 3:06am:@robg,
what do you mean by I also like tying the ends of R2 and R3 together gives better noise performance.
.Biasing a PMOS with an NMOS isn't such a great idea either, means systematic offset or any thing else in your mind?
@arron..I agree with you , this additional stage or a cap between vc1 and vdd are doing same job..
In general I found many people are bit reluctant to use this idea. Can you people suggest me any good idea for LDO to get midband psrr better than let's say 20dB
Bear in mind I'm reluctant only because I haven't had time to figure out how it works. With his idea the opamp output now sees Vgs of MN41, which is removed once from Vdd variations. I'm not sure that the benefit isn't just from doing that. Plus it hasn't been too much of an issue for me to get 100dB of DC rejection so I'm not included to solve a problem I've never had
. However, it might be a fine idea.
Regarding tying the resistors together - M2 and M3 are used to create equal current, but they contribute thermal noise. The noise can be reduced by making their Vgs-Vt larger, but you run out of headroom. It turns out the optimum way to use this headroom is to use identical resistors - they are already dropping ~600mV which is enough. The down side is that it uses more area. I'm sure you have seen the result before:
My concern with using MN41 to bias M2 and M3 is over corners. The current in MN42 will need to change a lot to provide the proper bias for M2 and M3. This may affect the stability of the loop. It is already on the edge since he has two poles in the opamp and another in M2 and M3.
For good AC power supply rejection I would compensate the opamp with a cap and resistor in series between VC2 and VDD. (The resistor adds a zero to cancel the first pole). This will help AC rejection assuming the cap between VC2 and VSS is small. This won't work well with a two-stage opamp so instead of the miller opamp I would use a folded cascode with a PMOS input pair.
[edit... sorry for all the edits after my original posts. I seem to be making more typos and confusing statements these days.]