wag_master
New Member
Offline
Posts: 8
Colorado Springs, CO
|
I got it working. Here's the code:
`include "discipline.h" `include "constants.h"
//-------------------- // demuxdr_1_4 // V1. 9/23/2014 TS // Added reset, made all pins differential except vcc. // Logic is vcc referenced with a pp swing of vswing // // - 1 to 4 demux // This models an active demux, not a t-gate type. // It uses an internal counter instead of external inputs // to determine which output is selected. // // Dp, Dn: Signal to be multiplexed (val) // CKp, CKn: Clock input (val) // Rp, Rn, Sp, Sn: Reset and set inputs (val) // Q0,Q1,Q2,Q3: Outputs (val,flow) // vcc: Supply voltage (val) // // INSTANCE parameters // vswing = p-p output voltage swing // tdel, trise, tfall = the usual [s] //
module demuxdr_1_4(Dp, Dn, Rp, Rn, CKp, CKn, Q0p, Q0n, Q1p, Q1n, Q2p, Q2n, Q3p, Q3n, vcc); input Dp, Dn, Rp, Rn, CKp, CKn, vcc; voltage Dp, Dn, Rp, Rn, CKp, CKn, vcc;
output Q0p, Q0n, Q1p, Q1n, Q2p, Q2n, Q3p, Q3n; electrical Q0p, Q0n, Q1p, Q1n, Q2p, Q2n, Q3p, Q3n;
parameter real vswing = 0.24 from (0:inf); parameter real tdel = 5p from [0:inf); parameter real trise = 10p from (0:inf); parameter real tfall = 10p from (0:inf);
real out0p, out0n, out1p, out1n, out2p, out2n, out3p, out3n; real vh, vl; integer x, x0, x1, x2, x3, cntr;
analog begin @(initial_step) begin // Since cntr=cntr+1 occurs before the case statement, // this makes the first one selected to be out0. cntr = 3; vh = V(vcc); vl = vh-vswing; out0p = vl; out1p = vl; out2p = vl; out3p = vl; out0n = vh; out1n = vh; out2n = vh; out3n = vh; end
if (V(Rp) > V(Rn)) cntr = 3;
@(cross( V(CKp)-V(CKn), 1 ) ) begin cntr = cntr+1; if (cntr > 3) cntr = 0;
x = V(Dp) > V(Dn);
vh = V(vcc); vl = vh-vswing;
// Do the demux function case (cntr) 0: begin out0p= vh*x + vl*!x; out0n= vh*!x + vl*x; $strobe("%r: Setting out0", $abstime); end 1: begin out1p= vh*x + vl*!x; out1n= vh*!x + vl*x; $strobe("%r: Setting out1", $abstime); end 2: begin out2p= vh*x + vl*!x; out2n= vh*!x + vl*x; $strobe("%r: Setting out2", $abstime); end 3: begin out3p= vh*x + vl*!x; out3n= vh*!x + vl*x; $strobe("%r: Setting out3", $abstime); end default: $strobe("%r: ***** demuxdr_1_4: Help! cntr = %d", $abstime, cntr); endcase end
V(Q0p) <+ transition( out0p, tdel, trise, tfall); V(Q0n) <+ transition( out0n, tdel, trise, tfall); V(Q1p) <+ transition( out1p, tdel, trise, tfall); V(Q1n) <+ transition( out1n, tdel, trise, tfall); V(Q2p) <+ transition( out2p, tdel, trise, tfall); V(Q2n) <+ transition( out2n, tdel, trise, tfall); V(Q3p) <+ transition( out3p, tdel, trise, tfall); V(Q3n) <+ transition( out3n, tdel, trise, tfall); end endmodule
|