Designer’s Guide Community

eternity

Junior Member

Offline

Posts: 28

Distortion components in SAR ADC output spectrum.Advice/Help needed
Dec 03^rd, 2014, 12:21pm

Hi all,
I am trying to plot the FFT of a 10 bit SAR ADC in Spectre. I could get a clean spectrum with ideal capacitors and ideal switches. So my coherent sampling setting is perfectly fine.
but by keeping ideal switches and replacing only the ideal caps with 65nm real mimcaps, i see very strong distortion components in the output spectrum. i used a range of unit cap values and i see mostly the same trend results.

i am not able to narrow down the actual causes of it. Any suggestions ideas or advices are most welcome

Eternity

Back to top

IP Logged

sheldon

Community Fellow

Offline

Posts: 751

Re: Distortion components in SAR ADC output spectrum.Advice/Help needed
Reply #1 - Dec 4^th, 2014, 8:21pm

Eternity,

More information would be useful. First, I would have expected
that replacing the ideal switches with transistors would cause more
issues than the replacing the ideal caps with real caps.
1) Is the DAC a thermometer DAC or is it a split DAC?
2) Is the distortion, sample frequency dependent or input
frequency dependent?
3) When you look at the DAC levels, does it settle before the
next comparator is latched?
4) If you pull just the DAC out and simulate it, drive it with a
sine wave from an ideal ADC, is there distortion?
5) What is happening with the backplate node of the device
capacitors?
6) ....

Sheldon

Back to top

IP Logged

loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: Distortion components in SAR ADC output spectrum.Advice/Help needed Reply #2 - Dec 4^th, 2014, 11:02pm divide the problem down, there is a DAC, a comparator and some control circuits. Where is the problem?
Back to top	Jerry Twomey www.effectiveelectrons.com Read My Electronic Design Column Here Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical IP Logged

eternity

Junior Member

Offline

Posts: 28

Re: Distortion components in SAR ADC output spectrum.Advice/Help needed
Reply #3 - Dec 5^th, 2014, 3:29pm

sheldon wrote on Dec 4^th, 2014, 8:21pm:

Eternity,

� More information would be useful. First, I would have expected
that replacing the ideal switches with transistors would cause more
issues than the replacing the ideal caps with real caps.- Yes, same here and thats why I am puzzled.
1) Is the DAC a thermometer DAC or is it a split DAC?- Split Type
2) Is the distortion, sample frequency dependent or input
� �frequency dependent? - been strict on project specs and so did not change. will try and see the effect
3) When you look at the DAC levels, does it settle before the
� �next comparator is latched?- Yes, the DAC levels are hit as the switches are ideal. This was cross checked.
4) If you pull just the DAC out and simulate it, drive it with a
� �sine wave from an ideal ADC, is there distortion?- The entire system was simulated with ideal caps and ideal switches. No distortion issues came up. The other sub blocks were also swapped with its respective system level verilog models. Distortion results when DAC(with real caps & ideal switches) was simulated with verilog models of other sub blocks.
5) What is happening with the backplate node of the device
� �capacitors?
Sorry, did you mean the bottom plate of capacitors where it was connected to switching logic block.
6) ....

� Sheldon

Back to top

IP Logged

eternity Junior Member Offline Posts: 28	Re: Distortion components in SAR ADC output spectrum.Advice/Help needed Reply #4 - Dec 5^th, 2014, 3:32pm loose-electron wrote on Dec 4^th, 2014, 11:02pm: divide the problem down, there is a DAC, a comparator and some control circuits. Where is the problem?- I am going to have to try what the other colleague suggested here. I will get back here soon. Thanks for your suggestion
Back to top	IP Logged

RobG

Community Fellow

Offline

Posts: 569
Bozeman, MT

Re: Distortion components in SAR ADC output spectrum.Advice/Help needed
Reply #5 - Dec 5^th, 2014, 4:14pm

I'm working through the same issues.

1) The mimcaps I'm using have bad parasitic capacitance on both plates. The comparator side of a split DAC should be insensitive to parasitics, but the other side isn't. Since you have a split DAC it could be this parasitic that is causing the problem.

2) The DAC is very sensitive to the value of the splitting capacitor and you can't realistically use unit caps for it. For my process, the calculated value of the capacitor displayed on the schematic does not necessarily match the simulated value between the terminals! Differences are between 0 and 6%!

Hopefully you can just look in the netlist and see what values are being used for the capacitors and the parasitics. Then you can model the parasitics and real values with ideal caps and see if that is it. My cap model is so convoluted I still haven't been able to figure out what values are being used from the netlist.

Please let us know what you find out.

Back to top

IP Logged

eternity

Junior Member

Offline

Posts: 28

Re: Distortion components in SAR ADC output spectrum.Advice/Help needed
Reply #6 - Dec 6^th, 2014, 12:47pm

Thanks so much for your input on this.
Though I am due replying for the suggestions of one of the colleague posted earlier, I leave my quick reply to you here before I write in detail about previous suggestions

RobG wrote on Dec 5^th, 2014, 4:14pm:

I'm working through the same issues.

1) The mimcaps I'm using have bad parasitic capacitance on both plates. The comparator side of a split DAC should be insensitive to parasitics, but the other side isn't. Since you have a split DAC it could be this parasitic that is causing the problem.
The news about this problem is simply a HORROR for me. I never knew this is going to be such a BIG issue especially even when the transistor based switches are not even there in the schematic yet..!!

2) The DAC is very sensitive to the value of the splitting capacitor and you can't realistically use unit caps for it. For my process, the calculated value of the capacitor displayed on the schematic does not necessarily match the simulated value between the terminals! Differences are between 0 and 6%! - Just to make it sure, do you mean that the value difference and hence the performance degradation is only due to bridge(center cap between MSB side and LSB side) capacitor in the DAC or all the capacitors in DAC.

Hopefully you can just look in the netlist and see what values are being used for the capacitors and the parasitics. Then you can model the parasitics and real values with ideal caps and see if that is it. My cap model is so convoluted I still haven't been able to figure out what values are being used from the netlist.- I have not done this procedure yet. I will try doing it and get back to you on this.

Please let us know what you find out.

General Query: If the parasitic caps are going to be this badly behaved, why almost none of the recent publications(considering here only the top publications) on high resolution SAR ADC never addressed this vigorously. Atleast I havent come across one yet so far.

Eternity

Back to top

IP Logged

RobG

Community Fellow

Offline

Posts: 569
Bozeman, MT

Re: Distortion components in SAR ADC output spectrum.Advice/Help needed
Reply #7 - Dec 6^th, 2014, 4:10pm

eternity wrote on Dec 6^th, 2014, 12:47pm:

General Query: If the parasitic caps are going to be this badly behaved, why almost none of the recent publications(considering here only the top publications) on high resolution SAR ADC never addressed this vigorously. Atleast I havent come across one yet so far.

I can't figure out why the caps I have to use are so bad. Normally the cap parasitic is just on the bottom plate. Hopefully you just have parasitics on the bottom, but the top parasitic is something to check for.

For your other question, the dac elements depend on the ratio of the capacitors. This is relatively easy to do if they are binary weighted. However, the splitting capacitor usually comes out to be a value that is hard to ratio.

Anyway, find out what the parasitics on your cap are and see if that is causing the issue.

Back to top

IP Logged

eternity

Junior Member

Offline

Posts: 28

Re: Distortion components in SAR ADC output spectrum.Advice/Help needed
Reply #8 - Dec 8^th, 2014, 6:37am

eternity wrote on Dec 5^th, 2014, 3:29pm:

sheldon wrote on Dec 4^th, 2014, 8:21pm:

Eternity,

� More information would be useful. First, I would have expected
that replacing the ideal switches with transistors would cause more
issues than the replacing the ideal caps with real caps.- Yes, same here and thats why I am puzzled.
1) Is the DAC a thermometer DAC or is it a split DAC?- Split Type
2) Is the distortion, sample frequency dependent or input
� �frequency dependent? - been strict on project specs and so did not change. will try and see the effectI checked with different sampling rate(much slower than before) and the trend of output spectrum is still the same and so the issue is definitely coming from caps.
3) When you look at the DAC levels, does it settle before the
� �next comparator is latched?- Yes, the DAC levels are hit as the switches are ideal. This was cross checked.
4) If you pull just the DAC out and simulate it, drive it with a
� �sine wave from an ideal ADC, is there distortion?- The entire system was simulated with ideal caps and ideal switches. No distortion issues came up. The other sub blocks were also swapped with its respective system level verilog models. Distortion results when DAC(with real caps & ideal switches) was simulated with verilog models of other sub blocks.
5) What is happening with the backplate node of the device
� �capacitors?
Sorry, did you mean the bottom plate of capacitors where it was connected to switching logic block.
6) ....

� Sheldon

Back to top

IP Logged

loose-electron

Senior Fellow

Offline

Best Design Tool =
Capable Designers

Posts: 1638
San Diego California

Re: Distortion components in SAR ADC output spectrum.Advice/Help needed
Reply #9 - Dec 8^th, 2014, 6:37pm

eternity wrote on Dec 6^th, 2014, 12:47pm:

General Query: If the parasitic caps are going to be this badly behaved, why almost none of the recent publications(considering here only the top publications) on high resolution SAR ADC never addressed this vigorously. Atleast I havent come across one yet so far.

Eternity

Many IEEE JSSC papers do not cover many of the "practical issues" associated with the design. Having been a reviewer for the JSSC a lot of the academics that review papers frown on practical issues, as long as the math looks pretty.

Problem with peer review journals is that many of the peers doing the review tend to be academics rather than active in industry.

Back to top

Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical

IP Logged

carlgrace

Senior Member

Offline

Posts: 231
Berkeley, CA

Re: Distortion components in SAR ADC output spectrum.Advice/Help needed
Reply #10 - Dec 11^th, 2014, 6:06pm

RobG wrote on Dec 6^th, 2014, 4:10pm:

I can't figure out why the caps I have to use are so bad. Normally the cap parasitic is just on the bottom plate. Hopefully you just have parasitics on the bottom, but the top parasitic is something to check for.

Hey Rob,

What process node are you using? �I recently did a high-speed pipeline in 65nm and the cap matching sucked. �It turned out that fringe cap was the killer and fringe isn't much better from the top plate than the bottom plate. �It was a multi-channel chip with really tight area constraints so I couldn't just spread out the routing. �We decided to just eat it and the customer accepted lower linearity than originally spec'd and we taped it out with a tight cap array anyway.

Does your model include fringe cap? �It has to make some pretty wild assumptions obviously because it doesn't have any specific knowledge of your routing. If it doesn't include routing be prepared for a sad couple of days when you extract your cap layouts the first time.

Back to top

IP Logged

RobG

Community Fellow

Offline

Posts: 569
Bozeman, MT

Re: Distortion components in SAR ADC output spectrum.Advice/Help needed
Reply #11 - Dec 11^th, 2014, 7:03pm

carlgrace wrote on Dec 11^th, 2014, 6:06pm:

RobG wrote on Dec 6^th, 2014, 4:10pm:

I can't figure out why the caps I have to use are so bad. Normally the cap parasitic is just on the bottom plate. Hopefully you just have parasitics on the bottom, but the top parasitic is something to check for.

Hey Rob,

What process node are you using? �I recently did a high-speed pipeline in 65nm and the cap matching sucked. �It turned out that fringe cap was the killer and fringe isn't much better from the top plate than the bottom plate. �It was a multi-channel chip with really tight area constraints so I couldn't just spread out the routing. �We decided to just eat it and the customer accepted lower linearity than originally spec'd and we taped it out with a tight cap array anyway.

Does your model include fringe cap? �It has to make some pretty wild assumptions obviously because it doesn't have any specific knowledge of your routing. If it doesn't include routing be prepared for a sad couple of days when you extract your cap layouts the first time.

I'm 28nm. They are finger caps so that is why both sides have the parasitic. What is odd to me is that the parasitic is about the same for a M4-M6 cap as a M1-M6 cap. Several years ago someone tried to convince me that going up to higher metal didn't help fringe cap and you seem to be saying the same ting. Why doesn't being farther from the substrate help?

Not looking forward to extraction...

Back to top

IP Logged

sheldon

Community Fellow

Offline

Posts: 751

Re: Distortion components in SAR ADC output spectrum.Advice/Help needed
Reply #12 - Dec 11^th, 2014, 7:58pm

Another thing that you should do is review the discussions
digital assist, calibration, to eliminate the accuracy issues
introduced by the capacitor variation and parasitics.
Calibration is pretty much required when using a split
cap DAC for high accuracy applications since the series
cap is not a unit capacitor, see
Yasuhide Kuramochi, Akira Matsuzawa, and Masayuki Kawabata
"A 0.05-mm2 110-uW 10-b Self-Calibrating Successive
Approximation ADC Core in 0.18-um CMOS" A-SSCC,
8-1, pp 224-227, Korea, Jeju, Nov, 2007

as an example of calibration. The next year there was a paper
on compensating for dynamic comparator offset at the same
conference

Sheldon

Back to top

IP Logged

DanielLam

Community Member

Offline

Posts: 76

Re: Distortion components in SAR ADC output spectrum.Advice/Help needed
Reply #13 - Dec 16^th, 2014, 10:25pm

When you say split cap, do you mean you use an attenuation capacitor? Or are you splitting capacitors into 2 halves to save power (no attenuation capacitor)?

If it is the attenuation capacitor, you should see distortion reduced by increasing the unit cap size (eg 10 fF to 100 fF). This leads me to think that you are splitting caps into two halves.

If it is the latter, try different types of caps to see if there is a difference. I have a feeling it might be the voltage coefficient.

Back to top

IP Logged

Lex

Senior Member

Offline

Posts: 201
Eindhoven, Holland

Re: Distortion components in SAR ADC output spectrum.Advice/Help needed
Reply #14 - Dec 17^th, 2014, 7:23am

RobG wrote on Dec 11^th, 2014, 7:03pm:

carlgrace wrote on Dec 11^th, 2014, 6:06pm:

RobG wrote on Dec 6^th, 2014, 4:10pm:

I can't figure out why the caps I have to use are so bad. Normally the cap parasitic is just on the bottom plate. Hopefully you just have parasitics on the bottom, but the top parasitic is something to check for.

Hey Rob,

What process node are you using? �I recently did a high-speed pipeline in 65nm and the cap matching sucked. �It turned out that fringe cap was the killer and fringe isn't much better from the top plate than the bottom plate. �It was a multi-channel chip with really tight area constraints so I couldn't just spread out the routing. �We decided to just eat it and the customer accepted lower linearity than originally spec'd and we taped it out with a tight cap array anyway.

Does your model include fringe cap? �It has to make some pretty wild assumptions obviously because it doesn't have any specific knowledge of your routing. If it doesn't include routing be prepared for a sad couple of days when you extract your cap layouts the first time.

I'm 28nm. They are finger caps so that is why both sides have the parasitic. What is odd to me is that the parasitic is about the same for a M4-M6 cap as a M1-M6 cap. Several years ago someone tried to convince me that going up to higher metal didn't help fringe cap and you seem to be saying the same ting. Why doesn't being farther from the substrate help?

Not looking forward to extraction...

You're not allowed to layout your own custom cell? If you can customize your fringe cap then you can select which wires to use for which fingers, which is quite rewarding. It opens lots of possibilities =) My experience (in 65nm) is that when the same kind of layout is followed, even the PDK mismatch data also translates reasonably well to the custom cell.

Back to top

IP Logged