cktdesigner
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Schematic of the ÷2OR3 dual-modulus prescaler along with code for each of the blocks.
This dual-modulus prescaler is taken from Razavi's RF Microelectronics 2nd Edition (p.679, Fig.10.31, Chapter 10, Sec 10.6).
Please note that when MC=0 the circuit divides by 3 and when MC=1 the circuit divides by 2.
code for DFF: `include "constants.vams" `include "disciplines.vams"
module adff (q, qb, clk, d);
output q; voltage q; // Q output output qb; voltage qb; // Q bar output input clk; voltage clk; // Clock input (edge triggered) input d; voltage d; // D input
real td; real tt; real vh; real vl; real vth; integer dir;
real state;
analog begin td = 0; tt = 1p; vh = 1; vl = 0; vth = (vh + vl)/2; dir = +1; @(cross(V(clk) - vth, dir)) state = (V(d) > vth); V(q) <+ transition( state ? vh : vl, td, tt ); V(qb) <+ transition( state ? vl : vh, td, tt );
end endmodule
Code for OR Gate: `include "constants.vams" `include "disciplines.vams"
module aor (out, in1, in2);
output out; voltage out; input in1, in2; voltage in1, in2; real vh; // output voltage in high state real vl; // output voltage in low state real vth; // threshold voltage at inputs real td; // delay to start of output transition real tt; // transition time of output signals
analog begin vh = 1; vl = 0; vth = (vh + vl)/2; td = 0; tt = 1p; @(cross(V(in1) - vth) or cross(V(in2) - vth)) ;
V(out) <+ transition( ((V(in1) > vth) || (V(in2) > vth)) ? vh : vl, td, tt ); end endmodule
Code for AND Gate: `include "constants.vams" `include "disciplines.vams"
module aand (out, in1, in2);
output out; voltage out; input in1, in2; voltage in1, in2; real vh; // output voltage in high state real vl; // output voltage in low state real vth; // threshold voltage at inputs real td; // delay to start of output transition real tt; // transition time of output signals
analog begin vh = 1; vl = 0; vth = (vh + vl)/2; td = 0; tt = 1p; @(cross(V(in1) - vth) or cross(V(in2) - vth)) ;
V(out) <+ transition( ((V(in1) > vth) && (V(in2) > vth)) ? vh : vl, td, tt ); end endmodule
The NOT gate in the schematic is realized as a NAND gate with both inputs tied together. The code for the NAND gate inside the NOT gate module in the schematic is shown below
Code for NAND gate: `include "constants.vams" `include "disciplines.vams"
module anand (out, in1, in2);
output out; voltage out; input in1, in2; voltage in1, in2; real vh; // output voltage in high state real vl; // output voltage in low state real vth; // threshold voltage at inputs real td; // delay to start of output transition real tt; // transition time of output signals
analog begin vh = 1; vl = 0; vth = (vh + vl)/2; td = 0; tt = 1p; @(cross(V(in1) - vth) or cross(V(in2) - vth)) ; V(out) <+ transition( !((V(in1) > vth) && (V(in2) > vth)) ? vh : vl, td, tt ); end endmodule
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