Hi,

I am new in calculating phase noise of a CMOS inverter ring oscillator with 6.24GHz to generate 3.12GHz, 25% duty cycle output using CML divider and AND gate setup. Can anyone help me how to select tstab value, maximum sidebands, no: of harmonics and output frequency sweep range with points per decade. As the phase noise result that i obtained shows -30db roll off till 1MHz and very low phase noise of -60dBc/Hz. is it the correct way?