Hi Guys,
Here is the problem. I have multiple verilog modules declared in a single cell view called function. One of them is the top module and the others are called in the top module. In this case can I just run without creating new cells or symbols for the sub-modules in Cadence?
If yes, what should be extra steps. Currently, the simulator complained elaboration erros:
Netlisting failed because the instance is bound to an invalid placed master Ensure that the specified placed master exists and is included in the list of reference libraries in the cds.lib file ...
The unresolved cells appear red in the config hierarchy editor.
Many thanks!