Hi, what does an '&' in an if statement in verilogA mean? When does the following return true:
for (bit=0;bit<`NUM_DAC_BITS; bit=bit+1) begin
           if (code & code_mask[bit]) begin

where 'code' increments after the for loop has run for all NUM_DAC_BITS. code_mask[bit] = 1,2,4,8,16,32,64,128 for i = 0...7. code = 1...255.