The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
May 22nd, 2019, 10:13am
Pages: 1
Send Topic Print
If statement VerilogA (Read 2294 times)
verilogGuy
New Member
*
Offline



Posts: 2

If statement VerilogA
Jul 11th, 2016, 1:17pm
 
Hi, what does an '&' in an if statement in verilogA mean? When does the following return true:
for (bit=0;bit<`NUM_DAC_BITS; bit=bit+1) begin
           if (code & code_mask[bit]) begin

where 'code' increments after the for loop has run for all NUM_DAC_BITS. code_mask[bit] = 1,2,4,8,16,32,64,128 for i = 0...7. code = 1...255.
Back to top
 
 
View Profile   IP Logged
verilogGuy
New Member
*
Offline



Posts: 2

Re: If statement VerilogA
Reply #1 - Jul 11th, 2016, 2:33pm
 
Sorted it! Brain dead this evening. Returns true when both bits are 1.
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2019 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.