Hi everyone

I have some questions about Verilog-A hidden state.
In usual transient simulation, Verilog-A hidden state is not a problem. But in PSS simulation, simulation fails  if hidden state exist because of syntax check.
Can anybody tell me why transient simulation is OK and PSS fails if hidden state exist?
Maybe algorithm of transient simulation and PSS simulation is different. I will be appreciate if anybody can tell me some details.

Best regards

ana2

Hi ken

Thanks for reply.

I understand now SpectreRF can not handle [local state variables] with ordinary differential equations.
Is that because Mathematical reasons or can be improved in future?

best regards
ana2