The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Jun 20th, 2019, 4:43pm
Pages: 1
Send Topic Print
Verilog-A hidden state in tran simulation and pss simulation (Read 1530 times)
ana2
Junior Member
**
Offline



Posts: 10

Verilog-A hidden state in tran simulation and pss simulation
Nov 23rd, 2016, 5:49pm
 
Hi everyone

I have some questions about Verilog-A hidden state.
In usual transient simulation, Verilog-A hidden state is not a problem. But in PSS simulation, simulation fails  if hidden state exist because of syntax check.
Can anybody tell me why transient simulation is OK and PSS fails if hidden state exist?
Maybe algorithm of transient simulation and PSS simulation is different. I will be appreciate if anybody can tell me some details.

Best regards

ana2




Back to top
 
 
View Profile   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2168
Silicon Valley
Re: Verilog-A hidden state in tran simulation and pss simulation
Reply #1 - Nov 23rd, 2016, 10:10pm
 
Back to top
 
 
View Profile WWW   IP Logged
ana2
Junior Member
**
Offline



Posts: 10

Re: Verilog-A hidden state in tran simulation and pss simulation
Reply #2 - Dec 5th, 2016, 7:47pm
 
Hi ken

Thanks for reply.

I understand now SpectreRF can not handle [local state variables] with ordinary differential equations.
Is that because Mathematical reasons or can be improved in future?

best regards
ana2
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2019 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.