The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Mar 28th, 2024, 6:05am
Pages: 1
Send Topic Print
SPICE Non Linear Capacitor Modeling (Read 1535 times)
HA
New Member
*
Offline



Posts: 4

SPICE Non Linear Capacitor Modeling
Jan 21st, 2017, 5:06pm
 
I am trying to define a verilog A element which has a user defined Voltage-charge relationship of the type V=a*Q+b*Q^2 (a and b are user defined constant). The element closest to this is capacitor (V=Q/C) which is straightforward to implement in VA by assigning current using ddt.
Can anybody help which is the best way to implement this system. I am not sure VA handles Q. THanks!!
Back to top
 
 
View Profile   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2384
Silicon Valley
Re: SPICE Non Linear Capacitor Modeling
Reply #1 - Jan 24th, 2017, 6:42am
 
Back to top
 
 
View Profile WWW   IP Logged
HA
New Member
*
Offline



Posts: 4

Re: SPICE Non Linear Capacitor Modeling
Reply #2 - Jan 24th, 2017, 11:08am
 
Thanks a lot Ken!!
I had actually seen this link before and this is the reason I am here (it was written to post any questions here).
I should have made my question more clear. I am trying to model an element in which we cannot represent charge as an explicit function of voltage. For e.g.,
V=a*Q+b*Q^2+c*Q^4
If i take its derivative, C=dQ/dV----> C=f(Q). Since i cannot express Q explicitly, i cannot write I<+ddt(Q).
Would really appreciate your comment on this.
Back to top
 
 
View Profile   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2384
Silicon Valley
Re: SPICE Non Linear Capacitor Modeling
Reply #3 - Jan 24th, 2017, 1:35pm
 
Oh, that is interesting. I think you model it as follows:

Code:
real q;
analog begin
    q = idt(I(cap));
    V(cap) <+ f(q);
end 



-Ken
Back to top
 
 
View Profile WWW   IP Logged
HA
New Member
*
Offline



Posts: 4

Re: SPICE Non Linear Capacitor Modeling
Reply #4 - Jan 25th, 2017, 10:06am
 
This works like a gem. Thanks for sharing this.  :)
I have one more question. If i connect this element in a ckt, say in series with normal capacitor (C1)...then KCL requires that dQ/dt of both the elements should be same.

    C1      C2 (self defined VA based cap)
----||------||------

If my transient signal has no dc level then Q as well as dQ/dt are same on both the capacitors. However, for a signal with an offset or with a dc level, only dQ/dt is same not the absolute charge Q since SPICE forces the middle potential to ground though gdcpath, thereby Q from C*V are different.

What should be the real picture. If someone do measurements on this ckt, will he sees the same? I checked with the simulation that if capacitors are leaky, the node potential equilibrate depending on the leakage resistance of the two capacitors.

Thanks

Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.