Frank_Heart
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Posts: 29
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Hi, yvkrishna,
If you use a dynamic latch, the integration time matters for noise reduction. All your choices would be 1) bigger input gm 2) bigger drain cap 3) higher voltage level for FN/FP.
For 1) you could use bigger input devices, or use PMOS&NMOS input pair, then pull down FN/FP then pull up them to longer the integration time. For 3), you can use higher supply for 1st stage, or use two flying cap to boost FN/FP to higher voltage before firing the CLK.
And I usually saw people using this kind of latch in high speed ADC, with noise level around 100~200uV. SNDR~70dB.
For your application, I guess you should use preamp+latch. Otherwise, as ULPAnalog mentioned, large input dependent cap could limit your THD below 80dB.
-Frank
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