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Spectre netlisting issue with config view (Read 1337 times)

AMS_ei

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Posts: 67

Spectre netlisting issue with config view
Mar 18^th, 2017, 9:45pm

Hi,

I have created a config view in which I have kept a subckt definition ( instance I39 as shown in the attachment) as verilog view.
When I generated a netlist by choosing a spectre simulator, I observed that name of the subckt for the instance I39 is vanished and a new word "subcircuit" appears in that place as shown in the attachment.

Could you please explain me is it the issue with the verilog view itself?
or some more settings are required to generate the netlist from config view?

Thank you.
Kind regards,

spectre_netlist_error.png

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Andrew Beckett Senior Fellow Offline Life, don't talk to me about Life... Posts: 1742 Bracknell, UK	Re: Spectre netlisting issue with config view Reply #1 - Mar 20^th, 2017, 8:19am Do you really mean verilog? Spectre can't simulate Verilog (it actually does support structural verilog, but this isn't supported from ADE - not normally needed in an ADE flow) - it does support Verilog A, but not generic Verilog. It's a circuit simulator, not a logic simulator. Regards, Andrew.
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AMS_ei Community Member Offline Posts: 67	Re: Spectre netlisting issue with config view Reply #2 - Mar 21^st, 2017, 6:01pm Thank you Andrew for your valuable inputs. Yes, I agree with you.
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