The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Mar 28th, 2024, 11:16am
Pages: 1
Send Topic Print
A simple question regarding some verilog code (Read 2227 times)
wandola
Junior Member
**
Offline



Posts: 24

A simple question regarding some verilog code
Apr 04th, 2017, 7:25pm
 
Hi all,

I am wondering for the following code, at the rising edge of clk
what is the output when A==0.

thanks. Smiley


//------------------
always @ (posedge clk or negedge rstn)
begin
   if(rstn==0)
           out <= 0;
   else begin
           if (A==1)
                 out<=IN1;
          else
                 ;
         end
End
Back to top
 
 
View Profile   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2384
Silicon Valley
Re: A simple question regarding some verilog code
Reply #1 - Apr 4th, 2017, 11:57pm
 
if rstn is 0 output is 0, otherwise it remains unchanged.

-Ken
Back to top
 
 
View Profile WWW   IP Logged
wandola
Junior Member
**
Offline



Posts: 24

Re: A simple question regarding some verilog code
Reply #2 - Apr 5th, 2017, 6:27pm
 
got it. thanks Ken
Back to top
 
 
View Profile   IP Logged
skyer
New Member
*
Offline



Posts: 3
CHINA
Re: A simple question regarding some verilog code
Reply #3 - Apr 21st, 2017, 12:06am
 
I think it is unchanged.
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.