I would like to know if it's possible to access the global variables in verilogA when I run a simulation. The uses are as follows :

1) variables can be used to change the internal parameters of the verilogA so that it can adapt to the settings without passing any voltage or current through a port which represents the change of variable. Sometimes the variable can be a delay, bit pattern or a frequency variable which could be difficult to pass to the verilogA file.

2) If the verilogA file is used for punching out data from a simulation into a file which is to be processed later on, the user has to run the simulations in series in case of corner simulations because the file gets over written. But if variables can be accessed in the verilogA, then it can be used as a string to modify the file name which enables user to run cross corner simulations in parallel.

I'm looking for a way to achieve the second option which would only be possible if verilogA file can access the variables.