Hi Mehdi,

I have two questions for you?

1- Mismatch analysis of what block you are interested in?

2- Are you going to do an MC analysis for a fully transistor level delta sigma?

tnx

**MehdiOranji wrote on Nov 13**^{th}, 2017, 8:40pm:Hello,

I want to simulate a continuous time sigma delta modulator SNDR with Monte-Carlo simulation in Cadence and see the histogram of the SNDR so as to figure out how the device mismatches impact the modulator performance. I have the output bit stream of the modulator quantizer, I have no idea how to fed the output to the monte-carlo simulation and end-up with the histogram showing "#counts vs. SNDR". I would appreciate it if someone let me know how to do that.

Regards,

Mehdi