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Aug 22nd, 2019, 7:48am
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Load limit on the TIEHI and TIELO cells (Read 686 times)
pkd
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India
Load limit on the TIEHI and TIELO cells
Feb 06th, 2018, 7:36pm
 
When I see the .lib of a TIEHI or TIELO cell, I see some maximum capacitance load limit at the output pin. Since there is no transition requirement for this cell, I am wondering why does this limit exist and how is this limit calculated.
The TIEHI cell is nothing but a diode connected PMOS, source connected to VDD, drain/gate connecting to the gate of an NMOS. Source of the NMOS at ground, drain to the gate of a PMOS whose source is VDD and drain is out output pin.
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