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SAR ADC SNDR degradation due to bins around DC (Read 4941 times)
niloun
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SAR ADC SNDR degradation due to bins around DC
Mar 25th, 2018, 2:09pm
 
Hi everyone

I have simulated an SAR ADC with an input sine near the nyquist rate using 128 points and I see several bins around DC which are degrading the SNDR. Would you please tell me what these bins are?

I don't believe that these bins are because of aliasing.

FFT for normalized Frequency:



FFT using bins:


Output of the ADC in the time domain:


Thanks.
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DanielLam
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #1 - Mar 28th, 2018, 9:48am
 
DC offset or power supply spurs. Given enough bins, I've ignored the first few for offset or maybe you can digitally subtract the mean out. If it is power supply spurs (which will be higher than a few bins, and will be in multiple bins), you need to fix that.
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sheldon
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #2 - Mar 28th, 2018, 10:44am
 
They appear to be the even order harmonics of the design. Try making it
differential and see if they go away.

Suppose that fin =49MHz for a 100MHz sampling frequency. The second
harmonic is at 98MHz, reflecting down to baseband it becomes -2MHz
(98MHz-100MHz). The function is even so -2MHz becomes 2MHz.

Even Harmonics, near dc and go up: dc (0, offset), 2MHz (2), 4 (4), ...
Odd Harmonics, neat the Nyqvist rate and go down:  49MHz(1), 47MHz(3), ...
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niloun
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #3 - Mar 30th, 2018, 5:21am
 
DanielLam wrote on Mar 28th, 2018, 9:48am:
DC offset or power supply spurs. Given enough bins, I've ignored the first few for offset or maybe you can digitally subtract the mean out. If it is power supply spurs (which will be higher than a few bins, and will be in multiple bins), you need to fix that.


Thanks Daniel. I have simulated the same structure with Fin/Fs=0.1, and those bins around DC didn't exist, So my guess is that it is not related to power supply. So as you said it can be DC offset.
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niloun
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #4 - Mar 30th, 2018, 5:50am
 
sheldon wrote on Mar 28th, 2018, 10:44am:
They appear to be the even order harmonics of the design. Try making it
differential and see if they go away.

Suppose that fin =49MHz for a 100MHz sampling frequency. The second
harmonic is at 98MHz, reflecting down to baseband it becomes -2MHz
(98MHz-100MHz). The function is even so -2MHz becomes 2MHz.

Even Harmonics, near dc and go up: dc (0, offset), 2MHz (2), 4 (4), ...
Odd Harmonics, neat the Nyqvist rate and go down:  49MHz(1), 47MHz(3), ...


Thanks Sheldon for the explanation. It is already a differential structure with Fin around 99 and Fs=200.

Here is the FFT for Fin/Fs=0.1. the bin in 0.2 is big but not that much:

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DanielLam
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #5 - Mar 30th, 2018, 9:57am
 
Is this top plate sampling? Stick an ideal buffer going into the comparator inputs, and let me know if the spurs go away.
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niloun
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #6 - Mar 31st, 2018, 9:17am
 
DanielLam wrote on Mar 30th, 2018, 9:57am:
Is this top plate sampling? Stick an ideal buffer going into the comparator inputs, and let me know if the spurs go away.


It is bottom plate sampling. Will adding buffer to the inputs help in the bottom plate sampling too? I think it will add a considerable capacitive load to the array since the unit capacitors are about 10fF.
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niloun
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #7 - Apr 1st, 2018, 2:48am
 
sheldon wrote on Mar 28th, 2018, 10:44am:
They appear to be the even order harmonics of the design. Try making it
differential and see if they go away.

Suppose that fin =49MHz for a 100MHz sampling frequency. The second
harmonic is at 98MHz, reflecting down to baseband it becomes -2MHz
(98MHz-100MHz). The function is even so -2MHz becomes 2MHz.

Even Harmonics, near dc and go up: dc (0, offset), 2MHz (2), 4 (4), ...
Odd Harmonics, neat the Nyqvist rate and go down:  49MHz(1), 47MHz(3), ...


If it is because of aliasing what is the solution in circuit design? Is it inevitable and I should use anti aliasing filter? or there are ways to solve it in circuit level design?

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« Last Edit: Apr 1st, 2018, 6:40am by niloun »  
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deba
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #8 - Apr 1st, 2018, 11:17pm
 
Hi,

In the problematic FFT, can you share what is Fin/Fs? Are you sure your signal is on a bin? Are you following coherent sampling?

https://en.wikipedia.org/wiki/Coherent_sampling
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niloun
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #9 - Apr 2nd, 2018, 12:17am
 
deba wrote on Apr 1st, 2018, 11:17pm:
Hi,

In the problematic FFT, can you share what is Fin/Fs? Are you sure your signal is on a bin? Are you following coherent sampling?

https://en.wikipedia.org/wiki/Coherent_sampling


Hi deba. It is a coherent sampling.

For 128 points I have used Fin/Fs=63/128=0.4921875 (Fs=200, Fin=98.4375).

For 1024 points I have used Fin/Fs=511/1024=0.4990234375 (Fs=200, Fin=99.8046875)

I have read some where that there is spectral leakage around DC bin as well as signal bin and the first 6 bins are ignored. However, I am afraid if it is because of aliasing.
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DanielLam
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #10 - Apr 2nd, 2018, 1:42pm
 
Ok, if you're unit caps are 10 fF, and you're bottom sampling, and the comparator input is normal, I don't think the ideal buffer (vcvs element in cadence) will do anything. Note, the ideal buffer has no capacitance.

If those are your harmonics (and they are odd), and they seem to be a function of frequency, then I might guess they are coming from your sampling switches. If you used ideal sampling switches, do the harmonics go away?
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niloun
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #11 - Apr 3rd, 2018, 1:01am
 
DanielLam wrote on Apr 2nd, 2018, 1:42pm:
Ok, if you're unit caps are 10 fF, and you're bottom sampling, and the comparator input is normal, I don't think the ideal buffer (vcvs element in cadence) will do anything. Note, the ideal buffer has no capacitance.


Thanks Daniel. Yes the structure is as you said. Inputs to the comparator are Vcm being sampled via two switches. I know that ideal buffer doesn't have capacitors, I thought that after using a real buffer the parasitic capacitors will cause problem.

DanielLam wrote on Apr 2nd, 2018, 1:42pm:
If those are your harmonics (and they are odd), and they seem to be a function of frequency, then I might guess they are coming from your sampling switches. If you used ideal sampling switches, do the harmonics go away?


If they are harmonics, they are even harmonics surprisingly(the output is approximately symmetric around the X axis), since I have calculated the frequencies. I will use ideal switches and inform you with the results (It might take a while, I am sorry).
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niloun
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #12 - Apr 3rd, 2018, 9:55pm
 
DanielLam wrote on Apr 2nd, 2018, 1:42pm:
If those are your harmonics (and they are odd), and they seem to be a function of frequency, then I might guess they are coming from your sampling switches. If you used ideal sampling switches, do the harmonics go away?


Hi Daniel. Thank you so much. I changed all of the switches into ideal switches and those unwanted bins are gone.



Now the output is even more symmetric about the X axis.

I use this structure for the input switches:



and I use minimum size complementary switches for other parts.

I am going to change the input switches to minimum size switches to see what will happen.

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DanielLam
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #13 - Apr 4th, 2018, 12:50am
 
ExclaimI have an idea of what your problem is. But I want to help you figure it out on your own.

Changing to minimum input sampling switches is never done (I design ADCs for a living). So you can save your time by not doing that.

To become a better designer, you need to get to the problem faster. Stop doing FFT sims for now, they take too long.

Look at the top plate voltages, and find a situation where the ideal switch and your switch mismatch heavily. Why is this happening?
What is causing the voltage drop mismatch?

By the way, do your input waveforms look like the left side picture, or the right side picture?
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waveforms.jpg
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niloun
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #14 - Apr 4th, 2018, 11:46am
 
DanielLam wrote on Apr 4th, 2018, 12:50am:
ExclaimI have an idea of what your problem is. But I want to help you figure it out on your own.

Changing to minimum input sampling switches is never done (I design ADCs for a living). So you can save your time by not doing that.

To become a better designer, you need to get to the problem faster. Stop doing FFT sims for now, they take too long.

Look at the top plate voltages, and find a situation where the ideal switch and your switch mismatch heavily. Why is this happening?
What is causing the voltage drop mismatch?


Thank you so much for the help.

It sounds that the inputs near the full scale show significant difference in two structures. while they act alike near the common mode.

Here is the top plate voltages for two structures near the full scale:
The left diagram is for ideal switches and the right one is for the real switches.


I think the problem is voltage dependent behavior of the switches connected to the comparator which will cause non-linearity. complementary switches were not a good choice and I must have chosen bootstrap switches for the inputs.


DanielLam wrote on Apr 4th, 2018, 12:50am:

By the way, do your input waveforms look like the left side picture, or the right side picture?


I use the left sine waves for the input.
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