polyam
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Hi,
I've designed a 2nd order SC delta-sigma modulator to support 10kHz signal bandwidth. The OSR is 256 resulting in a 5.12MHz oversampling frequency. The OTAs used for the integrators are overdesigned to properly settle down even for a 20-MHz oversampling frequency. Just giving some numbers (DC-gain=120dB, UGBW=220MHz, phase margin=64). all switches and quantizer are transistorized.
The fully transistorized modulator perfectly works with a sampling frequency of 5MHz when I apply an IDEAL non-overlapping clock signal. The modulator works also well when I increase the clock frequency to 20 MHz and integrating the noise over 40kHz (OSR still 246) again with an IDEAL non-overlapping clock frequency.
Now here is the problem!! I replaced the ideal non-overlapping clock signal with a transistorized one. The modulator works well when the master clock is 5.12 MHz. BUT when I increase the master clock to 20MHz, I see a severe SNDR degradation.
Does anyone have any idea to fix this issue? What causes this issue? (I'll post spectrum in different cases)
Thanks
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