Hi,

I am designing a 16-bit delta-sigma DAC to cover 3-MHz bandwidth. It consists of the interpolation filter, delta-sigma modulator, DAC and reconstruction filter.
Reconstruction filter generally consists of a switched capacitor filter followed by a buffer and a continuous time filter.
The interpolation factor is 128 and I am clocking the delta-sigma modulator at 800MHz.
I haven't seen any delta-sigma DAC paper at this sampling rate with such a structure.
Anyways,
1- Is it really feasible to have a delta-sigma DAC at this sampling rate? Assuming that the delta-sigma modulator operates at this rate (it is a placed and routed digital circuit), the main bottleneck is the switched capacitor filter.
If it is feasible, what is the rule of thumps for the unity gain bandwidth of the OTA used in the switched capacitor filter?

I am adding the block diagram of the DAC.

Thanks