**Jacki wrote on Mar 13**^{th}, 2019, 7:44am:Do you check if the output signal is stable ringing or the frequency is updating. Maybe your settling time is long, and in fact your oscillator has reached the steady state.

also I don't understand why you add a zero at your inverter.

Yes, I checked the output signal for >1.5usec (for the 550-MHz case)

and for ~130nsecs (for the 13-GHz case which itself takes a very long time for the 13GHz case with maxstep=1psec) in a simple transient analysis with maxstep for time set to 1psec. The output signal is stable and so is the frequency of oscillation (vs. time) when plot using the freq() function in the ADE calculator.

I used the following:

freq(VT("/out") "rising" ?xName "time" ?mode "user" ?threshold (0.5 * VAR("pvdd")))

where pvdd (=800mV) is the supply voltage of the inverter/entire VCO.

In fact the plot of the Fosc vs. time curve stabilizes pretty fast soon after oscillations start, within 10nsecs of start of simulation and does not change or droop or rise w.r.t time after 10nsecs or so for both cases.

I am trying to implement the ring oscillator topology shown in the attached picture. I observed the cliff effect (w.r.t varying Vc) when I was originally using xtors in place of the ideal 42ohm resistor.

I decided to replace the xtor to simplify things by replacing with a resistor.

This is a vco where the frequency of oscillation is controlled by the voltage applied to the gate of the nmos in the attached picture which in turn varies the effective load cap seen by each inverter and hence Fosc.