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Sep 17th, 2019, 7:52am
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Continuous time Sigma-delta ADC Integrator area and Fs (Read 137 times)
neoflash
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Continuous time Sigma-delta ADC Integrator area and Fs
May 25th, 2019, 8:07pm
 
If noise requirement is the same, which indicates the integrator R shall remain the same.

Also, assume SQNR is much better than circuit noise.

Can we say integrator C will scale linearly with 1/Fs sampling clock? The slower the Fs, the smaller the Cap?

Thanks,
Neo
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