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Oct 14th, 2019, 1:10pm
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Binary bus evaluation in CASE statement for VerilogA (Read 125 times)
Guile
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Binary bus evaluation in CASE statement for VerilogA
Jul 9th, 2019, 8:07am
 
Hello, I'm trying to create a DAC based on a real circuit. This will be used to speed-up sims of a bigger system.
I am using CASE to evaluate each input word and then assign the correct voltage value (based on sims results).
I have not been successful so far implementing the DAC with using CASE, it looks like it does not evaluate correctly the options.

Code:
input [2:0] i_ddrvrefctrlqnnnh;
output vref_a;
electrical vref_a;
electrical [2:0] i_ddrvrefctrlqnnnh;
analog begin
//@(initial_step) begin
//	@(i_ddrvrefctrlqnnnh) begin
       case(i_ddrvrefctrlqnnnh)
//        0 : vout= 0.1;
        001 : vout= 0.2;
        2 : vout= 0.3;
        3 : vout=0.4;
        4 : vout=0.5;
//        5 : vout=0.6;
//        6 : vout=0.7;
//        7 : vout=0.8;
		default : vout=1;
       endcase
	V(vref_a)<+(vout);
//	end
end

endmodule 



Some lines are commented as part of the trial/error I've been doing.
I commented the first CASE-option and the result is always the "default" value. If I do not comment the first CASE-option, it always take the first option, never the following ones.
The second CASE-option was put in binary mode, looking to have a result there (that's why the difference with the others)
I'm testing this in a DC sim in spectre.

Regards,
Guile
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« Last Edit: Jul 09th, 2019, 9:25am by Ken Kundert »  

Guilebaldo
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Ken Kundert
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Re: Binary bus evaluation in CASE statement for VerilogA
Reply #1 - Jul 9th, 2019, 9:20am
 
The case statement takes a simple integer argument, you have passed it an array of electrical values.

As a starting point, take a look at the dac in this.

-Ken
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Guile
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Re: Binary bus evaluation in CASE statement for VerilogA
Reply #2 - Jul 9th, 2019, 11:35am
 
Thank you Ken!
I took a look at your code,  but I'm looking now how to assign the analog-bus to an integer (for CASE evaluation)....I mean to translate the binary word to an integer value.....do I need to implement a FOR loop and sweep the binary combinations to convert the binary word? Is there a function/command in VerilogA for this translation?

Thanks again for the support!
Guile
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Ken Kundert
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Re: Binary bus evaluation in CASE statement for VerilogA
Reply #3 - Jul 11th, 2019, 7:18am
 
Yes, you either need the for loop (though if the size of the bus is small, as it is in your case, you can explicitly unroll the loop yourself).

There is no function in Verilog-A to do this.

The code I pointed to is a DAC, and the computed value, aout, is a real value. But you could rewrite the code so that aout is an integer that takes the values 0, 1, 2, .... Then you can process it with a case statement.

-Ken
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