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Aug 22nd, 2019, 2:58pm
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bandgap couldn't lock to Vref. (Read 212 times)
Jacki
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bandgap couldn't lock to Vref.
Jul 25th, 2019, 8:18am
 
Hello,

   I am simulating a classic sub-1V folded bandgap voltage reference circuit with the OTA. The OTA is good even if mismatch is added during the MC simulation. However the bandgap doesn't work at some MC statistic corners, and the input voltage of the OTA drops to ground. For the same MC statistic corner, OTA itself can work properly. Does anybody have the experience before? I use the current source to bias the OTA now, shouldn't have any startup issue. Any comments are highly appreciated.
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Jacki
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Re: bandgap couldn't lock to Vref.
Reply #1 - Jul 26th, 2019, 8:37am
 
I am pretty sure it is not due to the startup circuit, I have added one to guarantee the bandgap core circuit to avoid the all "zero" state.
In the statistic corner, I can see the mismatch of the input stage of the OTA, threshold voltage mismatch is around 5mV, but I don't think it is such a big issue.
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Jacki
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Re: bandgap couldn't lock to Vref.
Reply #2 - Jul 29th, 2019, 6:16am
 
I also check the loop gain in both positive and negative with phase margin, looks ok, but the input gate voltage of the NMOS transistor is always drops to zero.
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Jacki
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Re: bandgap couldn't lock to Vref.
Reply #3 - Jul 30th, 2019, 5:31am
 
Is the problem due to the simulator setup? Or do I run the MC simulation in a wrong way? Currently I run globalMC and localMC at the same time, from my understanding, it shouldn't be the problem.
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Jacki
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Re: bandgap couldn't lock to Vref.
Reply #4 - Jul 30th, 2019, 5:32am
 
By the way, if I only run localMC, it is fine.
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Jacki
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Re: bandgap couldn't lock to Vref.
Reply #5 - Aug 9th, 2019, 4:10am
 
As shown in the figure, basically it is just a simple bandgap, the ota is a folded one, just wonder why it is so sensitive to the mismatch. All of the PVT corner simulations are fine.
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bg_001.JPG
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Jacki
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Re: bandgap couldn't lock to Vref.
Reply #6 - Aug 9th, 2019, 4:22am
 
By the way, is it ok for the cascode transistor entering the linear region in the folded cascode ota? From my opinion, it is ok.
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Horror Vacui
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Re: bandgap couldn't lock to Vref.
Reply #7 - Aug 12th, 2019, 6:32am
 
Jacki wrote on Jul 26th, 2019, 8:37am:
I am pretty sure it is not due to the startup circuit, I have added one to guarantee the bandgap core circuit to avoid the all "zero" state.
In the statistic corner, I can see the mismatch of the input stage of the OTA, threshold voltage mismatch is around 5mV, but I don't think it is such a big issue.


I suggest to check the mismatch case only, where the BG did not work. The information that the input terminals of the opamp goes to ground, suggest me that the start-up circuit fails in that corner, and/or the loop gain is not enough in that corner. Double check that the start-up is really functioning. Just adding some startup circuitry might not work in all corners, and it could give you false sense of confidence.

Triode region for the cascode means that you have - much - smaller output resistance on your gain node, and therefore the gain if the amplifier will be compromised. You should be able to see this in small-signal analyses.
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Jacki
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Re: bandgap couldn't lock to Vref.
Reply #8 - Aug 13th, 2019, 6:48am
 
Hello,

   Thank you for your reply, it is the mismatch from the current mirror. I have found the problem. Now can achieve 0.8V - 3.6V supply voltage rang with PVT and MC. However, in MC still 2 of 200 samples cannot give good results, but I think this needs fine modification only.
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