Hi,
I am writing a verilogAMS model for dual clamper. It's simple voltage clamp with upper threshold(upclamp) of 180mv and lower threshold(dnclamp) of 50mv. When upper threshold is reached then Output voltage is pulled down to ground and when lower threshold is reached then output voltage is pulled up to VDD.

AMS model works fine on block level testbench but it starts chattering on top level and slows down the simulation drastically?

Here is my verilogAMS code:

Code:

`include "constants.vams"
`include "disciplines.vams"

module compClamp (COMP2PWM,VoutDivRC2,COMPclamp,AVDD,AGND);
	input COMP2PWM;
	input VoutDivRC2;
	inout AVDD;
	inout AGND;
	output COMPclamp;

	electrical COMP2PWM, VoutDivRC2, COMPclamp, AVDD, AGND;
	electrical dnclamp,upclamp;

	real gm_dnclamp;
	real gm_upclamp;

    parameter real dn_clamp_offset=50m;
    parameter real up_clamp_offset=180m;
  
analog begin

    @(cross(dn_clamp_offset-V(COMP2PWM,VoutDivRC2),0))
		;
	if((dn_clamp_offset-V(COMP2PWM,VoutDivRC2))>0)
		gm_dnclamp= 11.0m;
    else
		gm_dnclamp= 1.0n;

    @(cross(V(COMP2PWM,VoutDivRC2)-up_clamp_offset,0))
		;
	if((V(COMP2PWM,VoutDivRC2)-up_clamp_offset)>0)
   		gm_upclamp= 11.0m;
    else
		gm_upclamp= 1.0n;

	I(AVDD,dnclamp) <+ V(AVDD,dnclamp) * transition(gm_dnclamp,0,500.0p,500.0p);
	I(upclamp,AGND) <+ V(upclamp,AGND) * transition(gm_upclamp,0,500.0p,500.0p);

	I(COMPclamp,upclamp) <+ V(COMPclamp,upclamp)*gm_upclamp;  
    I(COMPclamp,dnclamp) <+ V(COMPclamp,dnclamp)*gm_dnclamp;
end
endmodule 

Can anyone suggest improvement in the model to achieve this functionality without any slowdown? Thanks.