Hi,
Following your guide-line (Predicting the Phase Noise of PLL-Based Frequency Synthesizers) we have created the phase domain model for our PLL. Those models require a certain parameters (fcorner, white_noise_spd, ...) to be measured on the real circuit and be used here. the question is when running the simulation (either noise or pnoise) to measure these parameters what frequency range we should integrate it for?

e.g. we have frequency divider (VCO frequency is 16GHz, 16G / 8 = 2G) and the bandwidth of the PLL is roughly 20MHz. The input reference frequency is 2GHz. How to measure fcorner and white_noise_spd.
Thanks,

Is there any particular function in the Cadence which can calculate corner frequency? Or should I post-process the data?