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Sep 19th, 2020, 11:57am
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Phase noise and SFDR measurement of a Digital to Frequency Converter (Read 112 times)
seriuswhite
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Phase noise and SFDR measurement of a Digital to Frequency Converter
Aug 20th, 2020, 12:18pm
 
Hi,
I am making a DFC which takes a reference clock (fref) 10GHz and generates output clock of frequency = (m/2^N)fref, where m is the digital code, and N is the resolution of the DFC. N = 10 in my case so the minimum output frequency = fref/1024. I have both digital and analog blocks in my design. The digital block generates fractional output frequency but contains a lot of spurs. The analog block is used to reduce the spurs but doesn't eliminate them completely. The digital part is implemented in Verilog, so I am using the AMS simulator.

I have the following questions:

1. How to obtain the phase noise/SFDR from the transient simulation output? Should I do post-processing of sampled transient waveform in MATLAB or can I do that in cadence itself? How to do it? Should I convert the Verilog code to VerilogA and then use pss+pnoise? Will the phase noise plot obtained from pss+pnoise also give the spurs? I wouldn't prefer to convert the Verilog code unless there's no other solution.

2. I need to get phase noise at an offset of 1KHz from the carrier. So that means I need to run the transient simulation for 1ms? Also, since I am interested in jitter of the order of 100fs, my max step in transient simulation should be <50fs. That would mean insanely large simulation time  :'(. Any remedies to reduce this simulation time?
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« Last Edit: Aug 21st, 2020, 12:26am by seriuswhite »  
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Ken Kundert
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Re: Phase noise and SFDR measurement of a Digital to Frequency Converter
Reply #1 - Aug 21st, 2020, 8:13pm
 
You might be well served by reading Predicting the phase noise and jitter of PLL-based frequency synthesizers.  It discusses strategies for efficiently performing jitter transient simulations.  The basic idea is to perform detailed SpectreRF simulations on the individual blocks to extract their jitter, and then replacing those blocks with models that include jitter. Models that include jitter rather than noise do not need an excessive number of time points and so can be quite efficient.

If you are going to represent the jitter in discrete (Verilog) models, you will need to set the time precision very tightly. Doing so will not slow your simulation, but it does limit the stop time. Even at the smallest resolution of 1fs, you will not have any trouble even with 100ms simulations.

-Ken
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seriuswhite
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Re: Phase noise and SFDR measurement of a Digital to Frequency Converter
Reply #2 - Aug 22nd, 2020, 10:36am
 
Thank you so much Ken!!!
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