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Oct 19th, 2020, 3:06pm
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How do you simulate or define DNL/INL for a 1-bit Delta Sigma ADC for a dc input (Read 115 times)
iVenky
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How do you simulate or define DNL/INL for a 1-bit Delta Sigma ADC for a dc input
Oct 02nd, 2020, 11:33am
 
Hi,

I am wondering if it makes sense to define a DNL/INL for a 1-bit delta sigma ADC (1-bit comparator) for a DC input? Since the data is processed after a digital filter and we could have a 1 LSB error (meaning if the input is like 1LSB + Δv, we could have 1LSB or 2LSB at the output of delta-sigma without a 1-1 mapping due to limit cycles unlike other ADC architectures where is a 1-1 mapping), is there a way to define DNL/INL for a DC input? Does it make sense?
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Life is a nonlinear system. The goal is to find a solution with the least error and not an exact solution.
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Rakesh
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Re: How do you simulate or define DNL/INL for a 1-bit Delta Sigma ADC for a dc input
Reply #1 - Oct 7th, 2020, 8:34pm
 
Single bit DSM inherently is linear as it has two points. So it doesnt give DNL of INL. However the amplifier nonlinearity etc can introduce nonlinearity.

Also for single bit DSM gain is not defined
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iVenky
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Re: How do you simulate or define DNL/INL for a 1-bit Delta Sigma ADC for a dc input
Reply #2 - Oct 12th, 2020, 3:50pm
 
Thanks Rakesh! Yes, so it means it makes no sense to define DNL/INL for a single-bit delta-sigma, right?
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Life is a nonlinear system. The goal is to find a solution with the least error and not an exact solution.
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