Thank you again for your very helpful answers Ken!Regarding t0:
it is working fine as the code is written above but I will follow your advice and then test it when I change the frequency from e.g. f1 to f2.
For this I am also using the VCO model that I found here.Regarding Charge Pump:
Yes, it is a Charge Pump that is used to raise a voltage above the supply.
I found a very helpful paper that I using as a reference and adjusting it accordingly.
It also uses an ideal transformer: https://www.mdpi.com/2079-9292/9/6/998
I am only modeling the Charge Pump stage, CPmodel in the paper above.
It is working pretty fine stand-alone where I enter the frequency as a parameter.
The problem is that I have to put it then in a regulated loop which sends clocks, that's why I had to adjust the model to track the frequency of the input clocks to make the model frequency dependent.
If I use the frequency as a parameter the Chargepump will increase the voltage even when there are no input clocks.Regarding the update of the frequency measurement:
The picture below shows the initial simulation that I had (regulated loop with several instances of the N-Stage).
I defined one Stage stand-alone to have an output voltage of ~4.7V . If I run one stage of the schematic stand-alone I also reach ~4.7V.
As you can see the regulated loop schematic simulation goes to ~3.3V, with the model it goes to ~4.7V.
The picture show the initial version where the frequency was not updated to 0.
I run another simulation with the updated frequency measurement, but then I had to add time_out_delay=6u because of Fmin, but then freq updates only after 6us which is too long and the output voltage increased again up to ~4.7V.Question:
So, now even when the frequency measurement goes to zero the output voltage continues increasing up to ~4.7V.
Any ideas about what could be the reason?