While modelling a VCDL need to instantiate 40 delay cells.

Following code gives error during compilation

// VerilogA for DLL_behavioural_vams, vcdl, veriloga

`include "constants.vams"
`include "disciplines.vams"

module vcdl(Phi, CK_in, Vctrl);
input Vctrl, CK_in;
electrical Vctrl, CK_in;
output [39:0] Phi;
electrical [39:0] Phi;

delay_cell dcell0(Phi[0], CK_in, Vctrl);


for(genvar i=1; i<40; i = i+1) begin
     delay_cell dcell(Phi[i], Phi[i-1], Vctrl);
end

endmodule

Log file contents :

Reading file:
       /user_data1/mtech/18IE34001/work_umc_180/DLL_behavioural_vams/vcdl/veriloga/ver
iloga.va
Reading file:
       /software/eda/cadence/installed_bds/SPECTRE171/tools.lnx86/spectre/etc/ahdl/con
stants.vams
Reading file:
       /software/eda/cadence/installed_bds/SPECTRE171/tools.lnx86/spectre/etc/ahdl/dis
ciplines.vams

Error found by spectre during AHDL compile.
  ERROR (VACOMP-2259): "for<<--? (genvar i=1; i<40; i = i+1) begin"
       "/user_data1/mtech/18IE34001/work_umc_180/DLL_behavioural_vams/vcdl/veriloga/ve
riloga.va",
       line 15: syntax error.
   ERROR (VACOMP-1814): Maximum allowable errors exceeded. Exiting AHDL
       compilation....

What is possibly going wrong  :-/?

getVersion()
"@(#)$CDS: virtuoso version 6.1.7-64b 12/16/2018 07:36 (sjfhw317) $"
getVersion("virtuoso")
"sub-version  IC6.1.7-64b.500.23 "

I added the for in generate ... endgenerate block. Still getting the same error ! Not sure what exactly is the problem...

// VerilogA for DLL_behavioural_vams, vcdl, veriloga

`include "constants.vams"
`include "disciplines.vams"

module vcdl(Phi, CK_in, Vctrl);
input Vctrl, CK_in;
electrical Vctrl, CK_in;
output [39:0] Phi;
electrical [39:0] Phi;

delay_cell dcell0(Phi[0], CK_in, Vctrl);

generate
for(genvar i=1; i<40; i = i+1) begin
    delay_cell dcell(Phi[i], Phi[i-1], Vctrl);
end
endgenerate

endmodule