The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Dec 5th, 2024, 5:50pm
Pages: 1
Send Topic Print
Dead Zone problem in PLL (Read 691 times)
rajasekhar
New Member
*
Offline



Posts: 7

Dead Zone problem in PLL
Jun 06th, 2023, 2:02pm
 
dear All-
Can anyone help me how to detect whether a PLL has any dead zone problems in the lab? I mean in the characterization? Also, what is the disadvantage of having a dead zone in design? I mean any effect on the jitter?

Thanks,
Raj.
Back to top
 
 
View Profile   IP Logged
smlogan
Community Member
***
Offline



Posts: 52
Boston, MA
Re: Dead Zone problem in PLL
Reply #1 - Jun 8th, 2023, 5:31pm
 
Dear Raj,

Since the dead-zone of a phase detector is commonly a fixed time width, if you examine the loop performance (i.e. output phase noise for example) using the same basic loop bandwidth but with a set of increasing reference clock frequencies, the presence of the dead-zone on a unit-interval basis will be increasing. Hence, its impact on the output phase noise will be more evident.

For example, if you start with a reference clock of 10 MHz, a loop bandwidth of 1 MHz and jitter peaking of < 1 dB, and a loop divider of, say, 8. Examine its phase noise and then compare it to the following 2 cases:

1. Loop bandwidth of 1 MHz, jitter peak < 1 dB, reference clock frequency of 20 MHz, divider of 4
2. Loop bandwidth of 1 MHz, jitter peak < 1 dB, reference clock frequency of 40 MHz, divider of 2

If the dead-zone of the phase detector is significant relative to periods of 1/10 MHz, 1/20 MHz and 1/40 MHz, its presence should be evident in the output phase noise. Intuitively, the presence of the dead-zone means that for phase differences between the reference clock and feedback clock that are within the dead-zone, the VCO will be running open loop and hence the low frequency phase noise will mimic the open loop VCO phase noise.

An alternative is to apply sinusoidal phase modulation with some amplitude Aj in UI to the reference clock at a frequency less than the loop bandwidth and measure the output phase modulation at the same frequency (a filtered measurement is preferred to reduce noise). As the amplitude Aj approaches the dead-zone of the phase detector, the output phase amplitude will no longer track the input phase amplitude.

I hope this helps Raj.

Shawn


Back to top
 
 

Shawn
View Profile   IP Logged
baohulu
Community Member
***
Offline



Posts: 44
china
Re: Dead Zone problem in PLL
Reply #2 - Nov 3rd, 2024, 10:47pm
 
smlogan wrote on Jun 8th, 2023, 5:31pm:
Dear Raj,

as you said below

" Intuitively, the presence of the dead-zone means that for phase differences between the reference clock and feedback clock that are within the dead-zone, the VCO will be running open loop and hence the low frequency phase noise will mimic the open loop VCO phase noise."




I want to know in the above case, how "low frequency" will the vco PN contribute to the pll PN. if the pfd dead zone time window is 100ps, and in your case, fref=10M, divider ratio=10, fvco=100MHz, then, what is the frequency range of the vco phase noise will be the pll phase noise?

thanks
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.