VBIC version 1.2.1 is at present being finalized. There is one minor model change, an ability to have separate forward and reverse saturation currents (implemented so that by default they are the same, hence the version is backward compatable with 1.2). The main updates are explicit addition of code that improves convergence. Given that different simulators have different algorithms for helping to get convergence previously this was assumed to be a simulator specific task. Explicit numerical limiting has how been added. The enhacements being implemented in this version are: // // 1. Functions redefined to work properly in Verilog-A, previously // they were substituted by special code to generate .va files // without function calls. // 2. Noise declarations added, consistent with 1.1.5 version. // 3. qb and qbp calculations protected from having argument of the // square-root go less than zero (this required very unusual // conditions and parameters to occur, and needless to say // this happened some times). // 4. Parameter names changed to lower case, this is what they are // in simulator implementations. // 5. log mapped to ln, this was done in generated code, but in // Verilog-A log is log_10, not log_e. // 6. The avalanche function was modified to protect against // numerical problems for forward and low reverse bias. // 7. Hard limits on the local temperature were added. This is // required to avoid numerical problems. // 8. The excess phase network has been defined in a simpler // manner, but is exactly equivalent to the previous version. // It is now done without an inductor. This is the transformation: // Itzf-V(xf2)-j*w*C*V(xf1)=0 // j*w*L*V(xf2)+V(xf2)-V(xf1)=0 // where C=TD and L=TD/3 is what was done. // Itzf=V(xf2)+j*w*TD*V(xf1) // V(xf1)=j*w*(TD/3)*V(xf2)+V(xf2) // node xf1: two VCCS (Itzf, V(xf2)) plus TD capacitor // node xf2: one VCCS (V(xf1)), TD/3 capacitor, 1Ohm resistor // 9. gmin added explicitly // 10. pnjmaxi added explicitly, diode type currents linearized // for values greater than pnjmaxi // 11. dissimilar forward and reverse saturation currents added, // for improved modeling of HBTs // 12. explicit post-processing code added for display results // 13. Verilog-A style modified to work with ADMS //