// Simple logic gates
//
// Version 1a, 24 November 2006
//
// Ken Kundert
//
// Downloaded from The Designer's Guide (www.designers-guide.org).
// Post any questions to www.designers-guide.org/Forum

`include "disciplines.vams"

//
// 2-input Nand gate
//

module anand (out, in1, in2);

output out; voltage out;
input in1, in2; voltage in1, in2;
parameter real vh = 1;			// output voltage in high state
parameter real vl = 0;			// output voltage in low state
parameter real vth = (vh + vl)/2;	// threshold voltage at inputs
parameter real td = 0 from [0:inf);	// delay to start of output transition
parameter real tt = 0 from [0:inf);	// transition time of output signals

analog begin
    @(cross(V(in1) - vth) or cross(V(in2) - vth))
	;

    V(out) <+ transition( !((V(in1) > vth) && (V(in2) > vth)) ? vh : vl, td, tt );
end
endmodule


//
// 2-input Nor gate
//

module anor (out, in1, in2);

output out; voltage out;
input in1, in2; voltage in1, in2;
parameter real vh = 1;			// output voltage in high state
parameter real vl = 0;			// output voltage in low state
parameter real vth = (vh + vl)/2;	// threshold voltage at inputs
parameter real td = 0 from [0:inf);	// delay to start of output transition
parameter real tt = 0 from [0:inf);	// transition time of output signals

analog begin
    @(cross(V(in1) - vth) or cross(V(in2) - vth))
	;

    V(out) <+ transition( !((V(in1) > vth) || (V(in2) > vth)) ? vh : vl, td, tt );
end
endmodule



//
// 2-input And gate
//

module aand (out, in1, in2);

output out; voltage out;
input in1, in2; voltage in1, in2;
parameter real vh = 1;			// output voltage in high state
parameter real vl = 0;			// output voltage in low state
parameter real vth = (vh + vl)/2;	// threshold voltage at inputs
parameter real td = 0 from [0:inf);	// delay to start of output transition
parameter real tt = 0 from [0:inf);	// transition time of output signals

analog begin
    @(cross(V(in1) - vth) or cross(V(in2) - vth))
	;

    V(out) <+ transition( ((V(in1) > vth) && (V(in2) > vth)) ? vh : vl, td, tt );
end
endmodule



//
// 2-input Or gate
//

module aor (out, in1, in2);

output out; voltage out;
input in1, in2; voltage in1, in2;
parameter real vh = 1;			// output voltage in high state
parameter real vl = 0;			// output voltage in low state
parameter real vth = (vh + vl)/2;	// threshold voltage at inputs
parameter real td = 0 from [0:inf);	// delay to start of output transition
parameter real tt = 0 from [0:inf);	// transition time of output signals

analog begin
    @(cross(V(in1) - vth) or cross(V(in2) - vth))
	;

    V(out) <+ transition( ((V(in1) > vth) || (V(in2) > vth)) ? vh : vl, td, tt );
end
endmodule



//
// 2-input Exclusive Or gate
//

module axor (out, in1, in2);

output out; voltage out;
input in1, in2; voltage in1, in2;
parameter real vh = 1;			// output voltage in high state
parameter real vl = 0;			// output voltage in low state
parameter real vth = (vh + vl)/2;	// threshold voltage at inputs
parameter real td = 0 from [0:inf);	// delay to start of output transition
parameter real tt = 0 from [0:inf);	// transition time of output signals

analog begin
    @(cross(V(in1) - vth) or cross(V(in2) - vth))
	;

    V(out) <+ transition( ((V(in1) > vth) ^ (V(in2) > vth)) ? vh : vl, td, tt );
end
endmodule



//
// 2-input Exclusive Nor gate
//

module axnor (out, in1, in2);

output out; voltage out;
input in1, in2; voltage in1, in2;
parameter real vh = 1;			// output voltage in high state
parameter real vl = 0;			// output voltage in low state
parameter real vth = (vh + vl)/2;	// threshold voltage at inputs
parameter real td = 0 from [0:inf);	// delay to start of output transition
parameter real tt = 0 from [0:inf);	// transition time of output signals

analog begin
    @(cross(V(in1) - vth) or cross(V(in2) - vth))
	;

    V(out) <+ transition( !((V(in1) > vth) ^ (V(in2) > vth)) ? vh : vl, td, tt );
end
endmodule