// Simple logic gates (with supply connections) // // Version 1a, 6 April 2009, Ken Kundert // based on the gates.va (gates without supply connections) // // Downloaded from The Designer's Guide (www.designers-guide.org). // Post any questions to www.designers-guide.org/Forum `include "disciplines.vams" // inverter module ainv (out, in, dd); output out; voltage out; input in; voltage in; input dd; voltage dd; parameter real td = 0 from [0:inf); // delay to start of output transition parameter real tt = 0 from [0:inf); // transition time of output signals integer lout; analog begin // make sure simulator sees the threshold crossing @(cross(V(in) - V(dd)/2)) ; // compute the logical value of the output if (V(in) > V(dd)/2) lout = 0; else lout = 1; // create an analog version of logical output V(out) <+ V(dd)*transition(lout, td, tt); end endmodule // // 2-input Nand gate // module anand (out, in1, in2, dd); output out; voltage out; input in1, in2; voltage in1, in2; input dd; voltage dd; parameter real td = 0 from [0:inf); // delay to start of output transition parameter real tt = 0 from [0:inf); // transition time of output signals integer lout; analog begin // make sure simulator sees the threshold crossings @(cross(V(in1) - V(dd)/2) or cross(V(in2) - V(dd)/2)) ; // compute the logical value of the output if ((V(in1) > V(dd)/2) && (V(in2) > V(dd)/2)) lout = 0; else lout = 1; // create an analog version of logical output V(out) <+ V(dd)*transition(lout, td, tt); end endmodule // // 2-input Nor gate // module anor (out, in1, in2, dd); output out; voltage out; input in1, in2; voltage in1, in2; input dd; voltage dd; parameter real td = 0 from [0:inf); // delay to start of output transition parameter real tt = 0 from [0:inf); // transition time of output signals integer lout; analog begin // make sure simulator sees the threshold crossings @(cross(V(in1) - V(dd)/2) or cross(V(in2) - V(dd)/2)) ; // compute the logical value of the output if ((V(in1) > V(dd)/2) || (V(in2) > V(dd)/2)) lout = 0; else lout = 1; // create an analog version of logical output V(out) <+ V(dd)*transition(lout, td, tt); end endmodule // // 2-input And gate // module aand (out, in1, in2, dd); output out; voltage out; input in1, in2; voltage in1, in2; input dd; voltage dd; parameter real td = 0 from [0:inf); // delay to start of output transition parameter real tt = 0 from [0:inf); // transition time of output signals integer lout; analog begin // make sure simulator sees the threshold crossings @(cross(V(in1) - V(dd)/2) or cross(V(in2) - V(dd)/2)) ; // compute the logical value of the output if ((V(in1) > V(dd)/2) && (V(in2) > V(dd)/2)) lout = 1; else lout = 0; // create an analog version of logical output V(out) <+ V(dd)*transition(lout, td, tt); end endmodule // // 2-input Or gate // module aor (out, in1, in2, dd); output out; voltage out; input in1, in2; voltage in1, in2; input dd; voltage dd; parameter real td = 0 from [0:inf); // delay to start of output transition parameter real tt = 0 from [0:inf); // transition time of output signals integer lout; analog begin // make sure simulator sees the threshold crossings @(cross(V(in1) - V(dd)/2) or cross(V(in2) - V(dd)/2)) ; // compute the logical value of the output if ((V(in1) > V(dd)/2) || (V(in2) > V(dd)/2)) lout = 1; else lout = 0; // create an analog version of logical output V(out) <+ V(dd)*transition(lout, td, tt); end endmodule // // 2-input Exclusive Or gate // module axor (out, in1, in2, dd); output out; voltage out; input in1, in2; voltage in1, in2; input dd; voltage dd; parameter real td = 0 from [0:inf); // delay to start of output transition parameter real tt = 0 from [0:inf); // transition time of output signals integer lout; analog begin // make sure simulator sees the threshold crossings @(cross(V(in1) - V(dd)/2) or cross(V(in2) - V(dd)/2)) ; // compute the logical value of the output if ((V(in1) > V(dd)/2) ^ (V(in2) > V(dd)/2)) lout = 1; else lout = 0; // create an analog version of logical output V(out) <+ V(dd)*transition(lout, td, tt); end endmodule // // 2-input Exclusive Nor gate // module axnor (out, in1, in2, dd); output out; voltage out; input in1, in2; voltage in1, in2; input dd; voltage dd; parameter real td = 0 from [0:inf); // delay to start of output transition parameter real tt = 0 from [0:inf); // transition time of output signals integer lout; analog begin // make sure simulator sees the threshold crossings @(cross(V(in1) - V(dd)/2) or cross(V(in2) - V(dd)/2)) ; // compute the logical value of the output if ((V(in1) > V(dd)/2) ^ (V(in2) > V(dd)/2)) lout = 0; else lout = 1; // create an analog version of logical output V(out) <+ V(dd)*transition(lout, td, tt); end endmodule // // 3-input Nand gate // module anand3 (out, in1, in2, in3, dd); output out; voltage out; input in1, in2, in3; voltage in1, in2, in3; input dd; voltage dd; parameter real td = 0 from [0:inf); // delay to start of output transition parameter real tt = 0 from [0:inf); // transition time of output signals integer lout; analog begin // make sure simulator sees the threshold crossings @(cross(V(in1) - V(dd)/2) or cross(V(in2) - V(dd)/2) or cross(V(in3) - V(dd)/2)) ; // compute the logical value of the output if ((V(in1) > V(dd)/2) && (V(in2) > V(dd)/2) && (V(in3) > V(dd)/2)) lout = 0; else lout = 1; // create an analog version of logical output V(out) <+ V(dd)*transition(lout, td, tt); end endmodule