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ncelab error (Read 4580 times)

Dipankar

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Posts: 59

ncelab error
Aug 04^th, 2009, 5:03pm

Dear All,

� � I am facing the following error in AMS at ncelab phase.

" .... Discipline resolution Pass...
Doing auto-insertion of connection elements...
NO_GOOD_PKT ), .ACK_processing( ACK_processing ), .......
� |
ncelab: *E,CUVNAS (./ihnl/XXXXX/ZZZZ/schematic/verilog.vams,540|10): segmentation of �a signal �between analog ports is illegal.... "

background : trying to run spice level simulation of a digital block with the CDK of std-cell used. Now when I use functional views of the cdk cells the simulation goes fine. But when I use schematic view of the cdk cells in certain modules I face the above issue. Agian for those certain modules if I �use functional view things go fine.

Can anyone help ?

With Thanks and Regards,
Dipankar.

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Riad KACED

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Posts: 93
Swindon, UK

Re: ncelab error
Reply #1 - Aug 12^th, 2009, 10:38am

Hi Dipankar,

I had a similar problem a few while back. It was actually a design problem where I was doing a digital check (check whether a signal was high or low) when simulated the design in the analog domain.

You can do some debugging by giving the -chkdigdisp argument
to ncelab to tell it to output details of the discipline resolution.

BTW, can you share more information about your design ? This is very likely to give us better ideas.

Cheers,
Riad.

Riad KACED
PDK, EDA Support Engineer.

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