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| Design | Last post | Topics | Posts |
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RF Design Discuss issues in RF design. |
 May 21st, 2019, 6:52pmIn: Re: NF simulation using o... By: Ken Kundert |
1594 | 6310 |
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Analog Design Discuss issues in analog design. |
May 8th, 2019, 8:03pm In: about metal fuse trimming... By: ZY He |
2716 | 12675 |
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Mixed-Signal Design Discuss issues in mixed-signal design. |
May 5th, 2019, 4:48am In: TSMC 65nm Calibre dummy i... By: allendmh |
916 | 3785 |
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High-Speed I/O Design Discuss issues in high-speed I/O design. |
Mar 20th, 2019, 11:49am In: BER measurement of CDR us... By: kazkou |
205 | 798 |
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High-Power Design Discuss issues in high-power, high-voltage, and high-current design. |
Oct 23rd, 2018, 5:30am In: Help for Power supply Des... By: jjjjjjjjjjjjjjjjjjjjjjjjjjjjj |
129 | 461 |
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Mixed-Technology Design Discuss issues in the design of MEMS and other mixed technologies. |
Feb 18th, 2018, 12:26am In: Working with Current in W... By: evan123 |
14 | 47 |
| Analog Verification | Last post | Topics | Posts |
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Analog Functional Verification Discuss analog, mixed-signal, and RF functional verification. |
Jul 31st, 2018, 11:23am In: Re: Help with a verilog-A... By: Ken Kundert |
58 | 220 |
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Analog Performance Verification Discuss analog, mixed-signal, and RF performance verification. |
Sep 11th, 2017, 1:26am In: Re: Uses of Macro in Veri... By: Gp |
46 | 143 |
| Measurements | Last post | Topics | Posts |
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RF Measurements Discuss RF measurements. |
Dec 18th, 2018, 3:58pm In: Power average vs Log ave... By: iVenky |
149 | 503 |
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Phase Noise and Jitter Measurements Discuss phase noise and jitter measurements. |
Apr 15th, 2019, 3:40am In: Re: Is "phase jitter" sho... By: subtr |
380 | 1410 |
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Other Measurements Discuss measurements not covered in other boards. |
Mar 2nd, 2019, 6:55am In: Re: Measure Equivalent In... By: Andrew Beckett |
112 | 350 |
| Modeling | Last post | Topics | Posts |
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Semiconductor Devices Discuss semiconductor device modeling. |
May 21st, 2019, 5:23am In: Re: Verilog-A model extra... By: Geoffrey_Coram |
306 | 1232 |
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Passive Devices Discuss passive device modeling. |
May 26th, 2018, 8:34pm In: mim cap EM simulation By: Soroush |
91 | 318 |
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Behavioral Models Discuss behavioral modeling. |
May 2nd, 2019, 10:09am In: Re: VerilogA-instantiatio... By: Anish |
311 | 1113 |
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Transmission Lines and Other Distributed Devices Discuss modeling of high-frequency distributed devices such as transmission lines, s-parameter n-ports, etc. |
Nov 30th, 2018, 10:03am In: step response of tranmiss... By: srinivasan0901 |
32 | 114 |
| Design Languages | Last post | Topics | Posts |
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Verilog-AMS Discuss Verilog-AMS. |
Yesterday at 6:28pm In: Re: zi_zp() is inaccurate... By: Ken Kundert |
1074 | 4398 |
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VHDL-AMS Discuss VHDL-AMS. |
Aug 8th, 2017, 1:33am In: Re: Hamster vhdl-ams Err... By: Andrew Beckett |
125 | 314 |
| Simulators | Last post | Topics | Posts |
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Circuit Simulators Discuss circuit simulators and circuit simulation issues. |
Apr 29th, 2019, 10:16am In: pnoise simulation of the... By: dog1 |
1881 | 7326 |
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RF Simulators Discuss RF simulators and RF simulation issues. |
Apr 15th, 2019, 12:39am In: Verilog-A Oscillator Phas... By: shico |
915 | 3824 |
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AMS Simulators Discuss AMS simulators and AMS simulation issues. |
May 16th, 2019, 11:18pm In: Re: Faile Elaboration - n... By: Andrew Beckett |
317 | 1202 |
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Timing Simulators Discuss timing simulators and timing simulation issues. Timing simulators are also known as reduced-accuracy or 'fast Spice' circuit simulators. |
Nov 3rd, 2018, 10:54am In: Re: what are the port in... By: Andrew Beckett |
24 | 56 |
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System Simulators Discuss system simulators and system simulation issues. |
Apr 26th, 2018, 2:53pm In: library files are screwed... By: maxcy |
59 | 188 |
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Logic Simulators Discuss logic simulators and logic simulation issues. |
Aug 28th, 2018, 11:14am In: what is the usage of the... By: liletian |
35 | 91 |
| Other CAD Tools | Last post | Topics | Posts |
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Entry Tools Discuss entry tools and entry tool issues. |
Aug 8th, 2018, 5:46am In: DRC error for Nwell resis... By: abhilash_172 |
218 | 710 |
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Physical Verification, Extraction and Analysis Discuss physical verification, extraction and analysis tools and their issues. |
Jan 29th, 2019, 6:25pm In: Re: Extract parameters fo... By: Ziauddin |
268 | 701 |
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Unmet Needs in Analog CAD Propose ideas for new tools, for extensions to existing tools, and for new uses for existing tools. |
May 20th, 2015, 2:17am In: Re: Dummy fill custom too... By: A Kumar R |
17 | 62 |
| General | Last post | Topics | Posts |
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Tech Talk Discuss technology, musings, trends, ideas, products, rumors, news, or whatever. |
Oct 18th, 2018, 7:26pm In: It's SiP (still) a trend... By: kalinski |
105 | 298 |
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News Read about the latest happenings of our site. Moderator: Forum Administrator |
Apr 15th, 2019, 8:41am In: Re: designers-guide.org h... By: Geoffrey_Coram |
30 | 78 |
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Comments and Suggestions Give comments and suggestions on how to improve this site, including suggestions of new discussion boards. |
Nov 9th, 2016, 7:00pm In: Re: Sorting forum questio... By: Ken Kundert |
56 | 171 |
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Opportunities Available employment opportunities. |
Apr 1st, 2019, 11:14am In: Fully-funded PhD in IC de... By: John Hu |
121 | 163 |
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Our users have made 49061 Posts within 12304 Topics.
The most recent post is Re: zi_zp() is inaccurate in Cadence Spectre (Yesterday at 6:28pm). View the 10 most recent posts of this forum.
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The newest member is Guilherme Theis. |
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