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Mar 21st, 2019, 9:15am
1  Simulators / RF Simulators / SpectreRF Front-end receiver measurements
 on: Yesterday at 8:03pm 
Started by MWJ1975 | Post by MWJ1975
Hi,


I would like to simulate the ip3, NF, 1dB, and any other performance metrics for the front-end receiver I have designed. It consists of an LNA, injection-locked oscillator (ILO), an envelope detector and a 50-ohm output buffer (In that order).  The LNA is tuned for 1830MHz, and the ILO is tuned for 915MHz to perform divide-by-2.

Could anyone provide useful documents or links for receiver simulations? Or even suggest how I would measure the NF of the RX? I have an input and output port connected, but I am confused about the frequency selection. Since the LNA and OSC are tuned to different frequencies.  

I have designed the receiver in TSMC 130 nm technology using SpectreRF simulator.

2  Design / High-Speed I/O Design / BER measurement of CDR using Cadence
 on: Yesterday at 11:49am 
Started by kazkou | Post by kazkou
HI,
I am new to Clock and data recovery, I need to design CDR from scratch.
I have some question for designing CDR.

Before we tapeout the chip, usually how to we know BER of our designed CDR? We get the BER through the simulation or we only need to get approximate value through calculation as described in "Verification of Bit-Error Rate in Bang-Bang Clock and Data Recovery Circuits" ?

How do we know the exact loop bandwidth of the CDR when doing pre-simulation(using cadence spectre/virtuoso) ?

Thank you

3  Design / RF Design / Re: Smith chart of λ/4 Transmission Line
 on: Yesterday at 5:19am 
Started by blue111 | Post by SantoS_Nano
Hi...

1. The location of the Zin and Zout on smith chart will depends on the impedance values. In the attached smith chart, I think, the locations were chosen randomly.
But from figure, you can observe that Zin>Zout and both are real (pure resistances).

3. Yes. In quarter-wave transformer case,  ZTline is geometric mean of Zout and Zin.
You can observe this result by simply substituting l=lambda/4 in basic "transmission line impedance equation".

4. Question can be more clear.
but scaling with Zo (50ohm) is for simplicity. it is like, ZTline is normalized with Zo (ZTline/Zo).

Regards...

4  Design / RF Design / Re: Designing a low noise amplifier using AWR microwave office  (Newbie/Student)
 on: Yesterday at 4:52am 
Started by townie | Post by SantoS_Nano
Hello,

First of all, i want to know about the subcircuit you are using in the design. whether it is just S2P file? or it is an amplifier model provided by the vendor?

Form the datasheet, i can understand that, you no need to add extra transmission lines and tuning (internally matched to 50 ohm).
you just need to follow the circuit provided in the datasheet (2nd page).

Coming to your schematic, you connected Vcc and RFout directly. In general, we should use decoupling capacitors for RF IN and RF OUT (1nF as shown in datasheet).

Just add add capacitors at input and output (as shown in datasheet) and simulate. you should get some positive gain.

Comment back with simulation results...

5  Design / Mixed-Signal Design / Stability analysis of a Bang-Bang CDR loop
 on: Mar 18th, 2019, 10:05am 
Started by Sumilak1994 | Post by Sumilak1994
Hi,
I am simulating the stability model of a Half Rate Bang Bang CDR, but am confused about the value for Kpd.

In most places, I found Kpd defined as a linear function of σ (sigma) as follows:

For Gaussian distribution: (1/σ)√(2/pi)

For Uniform distribution: 1/(σ2√3)

But, I am confused how this "sigma" relates to jitter - whether it's only the random jitter component or the deterministic jitter component or both.

Also, why is only the jitter component of the data and not the clock taken into consideration while determining the Kpd ?

I am in a bit of a fix.   Undecided





6  Design / RF Design / Smith chart of λ/4 Transmission Line
 on: Mar 18th, 2019, 7:33am 
Started by blue111 | Post by blue111
I came across the following slide on power combiner circuit and I have questions about it.

1. Why traverse across the upper half circle ? In other words, why is Zin located at the right side of Zout ?

2. Why when translating an impedance towards the generator we move clockwise around the chart ?

3. Why "ZT-line is the geometric mean of Zout and Zin." ?

4. Why overlay the Smith chart scaled for ZT on top of the Z0 Smith chart ?



7  Design Languages / Verilog-AMS / Re: simulating .va files in hspice
 on: Mar 18th, 2019, 7:18am 
Started by masoumeh | Post by Andrew Beckett
The main issue is that you have vth=0 on the instance line for the quantizer, and since the clock transitions between 0 and 1V, it never crosses the threshold. Set it to 0.5 instead.

You also have your rise, fall and delay for the clock source set to the ridiculously short 1fs. That is going to make the simulator slower by trying to follow these unrealistically short transition times. Similarly you should set tt on the quantizer instance to be greater than 0. So I would suggest:

Code:
VCLK	clk	0		pulse	0 1 100p 100p 100p 0.390625u 0.78125u

Xquantizer1		out		in		clk	quantizer	levels=3 vh=1 vl=-1 vth =0.5 dir=1 td=0 tt=100p 



I ran this in spectre (with the same netlist) and it then works fine. Even 100ps rise time/transition may be shorter than you really need if you've got a 1.28MHz clock. That said, for spectre it didn't affect the speed that much between 100p or 1n.

Andrew.

8  Design Languages / Verilog-AMS / Re: simulating .va files in hspice
 on: Mar 17th, 2019, 3:31pm 
Started by masoumeh | Post by masoumeh
Thank you for your comment, I edited the post.

9  Design Languages / Verilog-AMS / Re: simulating .va files in hspice
 on: Mar 17th, 2019, 3:12pm 
Started by masoumeh | Post by Ken Kundert
If you want help, it is probably best to simply show the .va and .sp files rather than force people to download and unpack them. Also, you should give the error message or at least describe what is going wrong.

The way it currently stands, you are expecting people to do a bunch of work before they have any indication as to whether they can help you or not.


10  Design / Analog Design / Re: CMFB loop bandwidth requirement for differential amplifier
 on: Mar 17th, 2019, 1:53pm 
Started by Salim2019 | Post by Salim2019
Dear friend,
Thank you very much for your reply
My CMFB loop is not stable as I came to know that it has higher GBW than the GBW of the differential amplifier and hence polse from differential introduced to it and degraded the stability.

Thus I am going to decrease the CMFB loop bandwidth to improve the stability

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