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Aug 22nd, 2019, 7:33am
1  Simulators / Circuit Simulators / Plotting On Resistance of a Bootstrapped Switch
 on: Aug 20th, 2019, 6:02pm 
Started by repah | Post by repah
How does one plot the on resistance of a bootstrapped switch ?

2  Design / Mixed-Signal Design / LDO Simulation Output Results
 on: Aug 20th, 2019, 4:37pm 
Started by repah | Post by repah
I attempted to design a PMOS Pass Transistor LDO and obtained the following result.

I set the reference voltage to about 650mv and did a DC simulation.

The regulated voltage starts up and then dies as the VDD is ramped up.

What could be causing this ?

Thank you.

3  Measurements / Phase Noise and Jitter Measurements / Phase noise measurement using E5052B
 on: Aug 19th, 2019, 9:32am 
Started by deba | Post by deba
Hi All,

E5052B from Keysight uses "PLL method" to measure phase noise. I am measuring the phase noise of a 100 MHz square wave clock using this instrument. The effective offset range of the instrument is mentioned as 10 MHz for a 100 MHz clock, roughly 10% of the input clock frequency.

I am interested in phase noise beyond 10 MHz. What does the instrument measures at these offset frequencies? Does it show amplitude modulation(AM) sidebands along with phase modulation(PM) sidebands?

4  Simulators / AMS Simulators / Re: oscilalting convergence residue w/ veriloga signal generator
 on: Aug 15th, 2019, 4:10am 
Started by Horror Vacui | Post by Horror Vacui
I was able to solve the problem by simplifying the layout used for extraction. Unfortunately I was not able to pinpoint anything in the design which has caused the issue.

Many thanks for your help and explanations, Ken!

5  Analog Verification / Analog Performance Verification / Re: Ocean memory management
 on: Aug 14th, 2019, 6:34am 
Started by danmc | Post by danmc
I'll reply to myself.  Turns out some of the waveform processing functions in Cadence have memory leaks in some conditions.  dft() is one of them.  So if the analysis loop does lots of calls to dft(), well, doing more by having the outer loop can make it fail.

6  Design / Mixed-Signal Design / Re: How to store the difference of 2 voltages on capacitor
 on: Aug 13th, 2019, 12:07pm 
Started by josvlsi | Post by subtr
Did you disconnect the capacitor and make it floating at any point of time? If you read how SAR ADC's work.
1. charge a cap by connecting V1 in parallel to it.
2. disconnect the cap's bottom plate from the ground. The cap still is charged to V1 and it's bottom plate is at Ground because it's V1 - Vcap.
3. Now you can disconnect your input source and Connect V2. Your output is V2 - Vcap or V2 - V1.


7  Design / Mixed-Signal Design / Re: LDO Simulation - Cadence - ILoad vs. Vout - Line Regulation
 on: Aug 13th, 2019, 11:53am 
Started by repah | Post by subtr
My approach is minimum number of simulations and maximum results. You should choose
DC simulation with ideal load current and get results for :
1. bias margins,
2. output voltage
3. reliability risks

AC Simulation for Stability, PSRR etc. should require your load current to be varied as LDO is non linear. The poles move with load current changes.

Your worst case regulation will be bad at worst case gain. So you will have to stabilize your LDO in order to even see the possible gain and regulation. Generally the stages go out of saturation to a low gain corner when stressed to max load, min supply, ss 125, min res corner. You would see that the bias margins are bad in this corner. This is because ss will enforce more overdrive requirement by previous stages and 125 will ensure the max vdsat.

In short you need to go around a small cycle of DC-AC to be really sure what your load regulation is. A first cut regulation can be achieved after biasing in DC simulation alone. And then sweeping load in the worst case I have mentioned above.

Step input regulation will require you to complete AC to see the dip due to current step and settling time. That's AC load regulation.

8  Analog Verification / Analog Functional Verification / Re: What is the PSD of noise generated using rdist_normal function?
 on: Aug 13th, 2019, 11:38am 
Started by subtr | Post by subtr
DIRAC DELTA
I currently find it hard to picture sampling of white noise by dirac delta train as :
1. It results in infinite PSD or Infinite Variance (All hell breaks lose)
2. Dirac delta trains rather than finite valued-finite width samples.

PULSE SAMPLING
ISF for my perspective looked like a gate which periodically opens and closes allowing noise to get sampled for an oscillator like a pulse. Pulse sampling was chosen to avoid infinite aliasing because if we had a periodc ISF train, then its fourier coefficients die down at high freq. Sum of Squares of the coeffiecients will be the multiplication factor on the white noise in the band. But then any pulse couldn't be it, but ISF.

BAND LIMITING
Definitely pulse sampling followed by the inverter's RC LPF-hold(say for a ring oscillator) results in a band determined by the RC (< Ts). Ignoring the above two para, we have a finite valued sample valid for one time period Ts and band limited to f<1/Ts.

In case you think, this thought could be erronous, let's not pursue it. Smiley I value your precious time. I'm also trying to construct a theory.

9  Analog Verification / Analog Functional Verification / Re: What is the PSD of noise generated using rdist_normal function?
 on: Aug 13th, 2019, 10:36am 
Started by subtr | Post by Ken Kundert
I could not follow your thinking. For one thing, the ISF is a characteristic of the circuit, not the signals, so it really does not apply here.

I think of it very simply. Imagine you start with a white continuous time stochastic process and you sample it at TS. Then by Nyquist the frequency characteristics of the sampled sequence should match those of the continuous time process for fTS. If you sample a white continuous time stochastic process at TS you will end up with a sequence of uncorrelated random value, same as if you generated the values with a random number generator. Hence, for fTS both of the sampled sequences will be white, just like the continuous time process.

-Ken

10  Design / Mixed-Signal Design / Capacitor Selection in Sigma Delta Modulators
 on: Aug 13th, 2019, 10:24am 
Started by repah | Post by repah
Hello,

I am designing 3rd Order, Single Bit, CIFF Discrete Time Sigma Delta Modulator.

How to select the capacitors sizes for this design ?

See attachment.

CT = total of ff - feedback capacitors.

I know how to select CS1 based on my noise requirements. But how do I select the other capacitors sizes like Cff(x) and Cs(x) etc.

Thank you.

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