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Apr 18th, 2019, 3:49am
1  Simulators / Circuit Simulators / Re: Montecarlo Analyses
 on: Yesterday at 1:52am 
Started by Salim2019 | Post by Andrew Beckett
Which IC version are you using (Help->About in the CIW will tell you)? Are you using ADE XL, or ADE Explorer/Assembler? If you're using ADE XL, do you have access to ADE Explorer/Assembler?

I'm asking so that I can give you a targeted response rather than a long and rambling one that covers the different situations when this is something that has improved over the years and in newer tools.

Kind Regards,

Andrew.

2  General / News / Re: designers-guide.org has been updated
 on: Apr 15th, 2019, 8:41am 
Started by Ken Kundert | Post by Geoffrey_Coram
I'm using Firefox 45, which is the latest version available on RHEL6 (we're moving to RHEL7, but we have to make sure all our other software runs properly on RHEL7).
Also Chrome 49 (49.0.2623.110) on Linux.

Chrome 73 on Windows looks fine.

3  Design / Analog Design / opamp simulation
 on: Apr 15th, 2019, 7:54am 
Started by blue111 | Post by blue111
For improving phase margin of opamp3.asc , I use an extra series 5k resistor R1 to put a zero near the unity gain frequency.
but then, good accurate resistor is hard to fabricate.

So, let me ask: anyone have any idea on how to replace both the ideal current source and the extra resistor with a mosfet in ohmic region without using any extra bias voltage source ?

In other words, is it possible to use constant gm bias circuit in both opamp3.asc and opamp.asc circuit ?


4  Measurements / Phase Noise and Jitter Measurements / Re: Is "phase jitter" short term jitter or long term accumulated?
 on: Apr 15th, 2019, 3:40am 
Started by Homer | Post by subtr
I don't think I have heard the term called phase jitter. Jitter is a representation of the inconsistency in timing of the noisy output clock with respect to an ideal clock which should have been absolutely based on the period dictated by the input or the autonomous system.

Now this randomness can be represented as samples whose magnitudes at each of the timing edges represents the difference between the noisy edge and the ideal edge. This being a waveform in time has a frequency representation. The random nature of this waveform only lets us represent it in power spectral density format. This frequency domain representation is called phase noise.

Now every random noise has 2 representations which put together define it. First is the shape of PSD and second is the shape of magnitude density function(MDF). PSD for white noise is flat, flicker is 10dB/decade. PSD for an ADC quantization noise is assumed to be white.
While MDF for uncalibrated mismatch, phase noise, voltage noise etc. is gaussian, the quantization noise is assumed to be uniform.

You can find variance from intagrating PSD or from MDF directly using probability theory. In fact PSD only tells how the same noise power is distributed in frequency. Noise power can be seen as variance of voltage/phase etc. which is why the term noise power.

Now based on long term or short term, you can apply a sinc filter represented by (1-z^(-t/T)). For t=T, we get a simple high pass filter. This means you look at one period jitter when you integrate by applying this filter on the phase noise plot. You can also think that the duration for which we see actually limits the effect of lower frequency noise to even appear effectively becoming a high pass filter. By increasing the time duration for which you're looking at the accumulated noise, your HPF cut off goes towards DC.

5  Design / RF Design / Moved: Verilog-A Oscillator Phase noise
 on: Apr 15th, 2019, 12:39am 
Started by shico | Post by shico
This Topic has been moved to RF Simulators by Ken Kundert.

6  Simulators / RF Simulators / Verilog-A Oscillator Phase noise
 on: Apr 15th, 2019, 12:39am 
Started by shico | Post by shico
Hi,

I have an verilog-A oscillator which has a certain jitter. Using transient simulation I can get the period jitter which matches the input jitter to the model. But I would like to have the phase noise across frequency of this model. I know I can't use PSS noise but not sure how to get it using transient simulation. Can anyone help?

Thanks

Regards,
Sherif

7  Design / Analog Design / Re: current gain temperature coefficient of BJT.
 on: Apr 12th, 2019, 7:28am 
Started by Jacki | Post by Jacki
Solved, actually it is quite clear if we look at Vbe = VT/n * ln(Ic/Is), if we consider Ic/Is as the current gain, and Vbe has the CTAT characteristic, we can clearly get Ic/Is is a CTAT.

8  Simulators / RF Simulators / Re: question on pnoise sim theory
 on: Apr 12th, 2019, 2:19am 
Started by dog1 | Post by dog1
Hello Ken,

Thanks very much for your reply. Now it is clear for me:)

Best regards,

Chen

9  General / News / Re: designers-guide.org has been updated
 on: Apr 11th, 2019, 3:06pm 
Started by Ken Kundert | Post by Ken Kundert
I checked Firefox 52, 54, and 66 as well as Chrome 73, and all looks normal.

However, I also tried Internet Explorer 11, and it does look like your screen shots.

Frankly, life is too short to worry about Internet Explorer.

-Ken

10  General / News / Re: designers-guide.org has been updated
 on: Apr 11th, 2019, 12:59pm 
Started by Ken Kundert | Post by Ken Kundert
Thanks Geoffrey.
   I also was baffled by 'User CP', and only recently discovered it means 'User Control Panel'.

I also use Firefox and Chrome, and things look fine on my browsers. But the look of the browser is different. I am using an older Firefox and a recent Chrome. How about you?

-Ken

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