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Jun 27th, 2022, 11:47pm
1  Design / Analog Design / Re: Differential pair question
 on: Jun 24th, 2022, 7:40am 
Started by tenso | Post by bluejay

You are that M1 will be saturation throughout, whereas M2 is in cutoff when VG2 is 0, in saturation when VG2 is VDD/2 and in triode when VG2 is VDD.

But the output will not be exactly zero for VG2=VDD. It will be a small value close to the overdrive of M2 because some current is still flowing through this branch.
Also when both input voltages are VDD/2, ideally Vout should be VDD/2 for single ended configuration as in this picture, and Vout is zero for a fully differential output, as for a fully differential structure the output Vout = Vout1-Vout2.

So in the given picture Vout = VDD-Vov4, when VG1=VG2 = VDD/2,    where Vov4 = VGS4 - Vth4 = overdrive voltage of M4.

Attaching a simulated plot of the same. Vin and Vo are shown with currents of both branches. In the plot M0 corresponds to M1 in the picture with VG=VDD/2, and M6 from the plot is the same as M2 of picture, with VG2 being swept from 0 to VDD as indicated by the ramp.
Note the VDD here is 1V.

2  Simulators / AMS Simulators / Xcelium: How to insert different Interface Elements for different pins
 on: Jun 22nd, 2022, 6:52am 
Started by FelixDesigner | Post by FelixDesigner
I'm currently developing some Verilog-AMS models for analog circuits, in which I'm modelling analog signals using wreal types. So a typical module might look like the following:
module myblock ( vin,  iout );
  input vin;
  wreal vin;
  output iout;
  wreal iout;

I'm simulating these blocks both on top level, where all blocks are wreal models, and on block level, where this block will be used in a schematic view with Spectre components.

In the latter case, I need to set up the interface elements correctly. The difficulty is that some pins operate in voltage mode while others operate in current mode. That means the interface elements need to have different settings in each case, mainly in the currentmode setting.

In the Xcelium command-line flow, I could define something like this in my amscf.scs:
amsd {
        ie vsup=1.8 cellport="" currentmode=0
        ie vsup=1.8 cellport="myblock.iout" currentmode=1

In ADE, I would go to the Interface Element Setup window and select each pin to define the scope, then set the correct options.

However, in each case I have to point specifically at each pin to tell the simulator what type of IE it needs. This is very cumbersome and error-prone in a large design where there might be dozens of pins. Is there a way to define something in the Verilog-AMS code that will tell the simulator what type of IE needs to be inserted? For example, to define pins as wreal_v and wreal_i? Or can I somehow tell the simulator to use different settings for pin names starting with "i"?

3  Other CAD Tools / Physical Verification, Extraction and Analysis / Re: Cap extraction of an IC  PAD
 on: Jun 21st, 2022, 7:12am 
Started by vlsi_design | Post by Maks
Yes - do LVS and extraction using layout only, without doing cross-referencing to schematic - and you can get your parasitics for your design (do not create shorts or opens, or other wrong things - in which case, the results will be meaningless).

4  Design / Mixed-Signal Design / How to understand the binary-weighted SARADC
 on: Jun 17th, 2022, 12:16pm 
Started by Jacki_2016 | Post by Jacki_2016

   Probably my question is a bit old topic, but recently I found I may not understand it clearly. Let's take the bottom-plate sampling SARADC as the example, the binary-weighted is 2^N, N is integer. If we look at 5-bit SARADC, the capacitor array is 2^4 + 2^3 + 2^2 + 2^1 + 2^0 = 16 + 8 + 4 + 2 + 1 = 31, if we add the dummy LSB cap in the cap array, we have 32 unit caps in the cap array. That is what I understand the binary-weighted SARADC for bottom-plate sampling.
   However, recently, I saw a SARADC without the dummy LSB cap in the cap array, and it is bottom-plate sampling, the designer explains the binary-weighted means as long as the caps in the cap-array are binary-weighted, then it is called binary-weighted SARADC. I am thinking if we don't have the dummy LSB cap, can we really achieve the LSB based on the binary-weighted calculation?
   By the way, in the top-plate sampling, due to the parasitic cap in the cap-array, we can reuse the parasitic cap as the dummy LSB cap based on my understand, but not for the bottom-plate sampling.
   Any comments or suggestions on my confusion? Please correct me if I misunderstand the binary-weighted cap array in the SARADC.
   Thank you.

5  Design / Mixed-Signal Design / Performing Monte-Carlo simulation with AMS
 on: Jun 16th, 2022, 9:50am 
Started by sutapanaki | Post by sutapanaki
I am relatively new to working with AMS. However, I have a design with a digital block that if simulated with its schematic view with spectre, takes a week to finish. Substituting the digital with its RTL and running AMS takes just a few hours. I have run transient simulation this way and it runs ok, I can get the results from the expressions I have defined.
I wanted to also run MC with AMS (and ICRP mode) and here I was not very successful. I use the same testbench as for the transient AMS simulation, just choose the MC setup and also the ttg_localmismatch models. However simulation itself produces pretty much garbage. and as a result also the expressions don't evaluate. For ex, I have a verilog file generating stimuli for the test bench. In MC sims, all outputs of that block are 0, while they are as they should be when running just regular transient simulation with AMS.

I was wondering if there is anything different I should set up for the MC simulation now, when I am using the AMS - different, I mean, compared to non-AMS simulations? Is it at all possible to run MC with AMS?


6  Design / Analog Design / Reference Buffer for below ground voltages.
 on: Jun 15th, 2022, 6:48pm 
Started by saqibshah | Post by saqibshah
I am currently working on the design of a reference buffer for a Sigma Delta.
I came across the TI ADS1248(datasheet). It seems that the chip can accept negative voltage references below ground (AVSS-100mV), as well as postive voltage references above AVDD (AVDD+100mV).
Doing this with a normal unity gain OPMAP would seem impossible (cannot drive the outputs completely to either rail). Does anyone have some sort of idea, of how such a thing can be accomplished? Seems a swtiched cap front might be able to do it, albeit at the cost of an input current.


7  Analog Verification / Analog Performance Verification / Re: Start-up failures of a ring oscillator
 on: Jun 14th, 2022, 9:49pm 
Started by polyam | Post by Ken Kundert
I'm not exactly sure what you mean by "simulating start up failure".  Presumably you are trying to give it a good kick to get it started and see if it can sustain the oscillation?

I have see people use three ways to start an oscillator:
1. using initial conditions
2. using a tickler source
3. using transient noise

Using transient noise is the least reliable and least efficient.  Using initial conditions tends to work very well for ring oscillators.  Using a tickler source tends to work less well because people often put the source on the supply, and the mode of oscillation is not very sensitive to perturbations on the supply.  This is particularly true for differential ring oscillators.

If the oscillation does not sustain, it still might not be an issue with the circuit.  Simulators can exhibit numerical damping.  To reduce the chance that the simulator quenches the oscillation due to numerical damping, set maximum time step to get at least 30 time points per cycle and switch the integration method to trapezoidal rule.


8  Analog Verification / Analog Performance Verification / Start-up failures of a ring oscillator
 on: Jun 14th, 2022, 6:48pm 
Started by polyam | Post by polyam

Can anyone suggest a way of simulating start-up failures for a ring oscillator. Regardless of the type of the ring (although I am mostly interested in the inverter based ring oscillator) how can I do such a simulation in a noiseless conditions? Normally what I do, I add initial conditions to the simulation and run the transient sim without thermal noise being on. However, not quite sure if that's really the way simulate the start-up failures when running for example monte-carlo simulation. Any thought will be appreciated


9  Design / RF Design / Moved: Cadence Layout Cannot Show PDK Instance Graph
 on: Jun 8th, 2022, 9:07pm 
Started by ovicovic | Post by ovicovic
This Topic has been moved to Entry Tools by Ken Kundert.

10  Other CAD Tools / Entry Tools / Re: Cadence Layout Cannot Show PDK Instance Graph
 on: Jun 8th, 2022, 9:07pm 
Started by ovicovic | Post by ovicovic
The Q3 pic is below

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