hi，all！
To analyze the pole-zero effects, I also attempted to perform a PZ simulation (Pole-Zero analysis), the results of which are attached.

Hi all, I have encountered some challenging issues:

(1) When performing STB simulation analysis on an OPA with a feedback loop, I observed: When VDD <5V, the phase curve appears normal. However, when VDD >5V, the low-frequency phase approaches 0°. The circuit schematic and simulation results are attached.

It should be noted that the differential pair in the circuit is not operating in the saturation region (to minimize the minimum operating voltage). This circuit was originally designed to operate at VDD <5V. I attempted to modify its process  to enable operation at higher voltages (e.g., 7V).

(2) For a chopper-stabilized operational amplifier with a feedback loop consisting of multiple switched capacitor networks (selecting different capacitor groups at different time intervals), I encountered similar low-frequency phase approaching 0° phenomena when performing stability analysis using PSS+PSTB simulations.

As a newcomer to this field, I'm unable to determine the root causes or solutions. I sincerely hope to receive valuable suggestions from experienced colleagues.

hi, all
I simulate with spectre x, now, I have done the phase noise simulation with post rcc extraction netlist. but in the noise summary, the parasitic r is shown with G1bI_RCNet_xx， I have checked the "write RCNet box" in noise summary, but there is no description of the relationship between "G1bI_RCNet_xx" and the extracted rcc netlist, how can I know which net  "G1bI_RCNet_xx" corresponds to ??

thanks

Hi everyone,
I am new to system verilog modeling and my task is to model the 741 opamp using system verilog in as much detail as possible.

I was able to create a simple verilog description code, but the ADE simulator does not support simulating system verilog, a "corrupt netlist" notification pops up and after going through a couple of online material apparently spectre does not simulate system verilog.

Could some one recommend the appropriate steps to simulate the same on ADE or if there is an alternate tool that can be used?

FYI. I am limited to the DFII framework on cadence through the license my university uses. Other AMS tools are unavailable to me.

Thank You.

Hello!

I'm working on a very similar module, modeling a commercialized oscillator as a CW sine wave source. I'm seeing a problem on discontinuity and aliasing, although I have set Cadence's min. time step to only 1ps. Since I'm modeling a 5GHz CW source, how should I define the tt here accordingly? Should tt be way smaller than the period of such sine wave? Thank you!

As a reference, here's the code:

Code:

`include "disciplines.vams"
`include "constants.vams"

module CW_source(out);
	voltage out;
	output out;
    // Parameters for configuration
    parameter real freq_center = 5e9; // Center frequency in Hz
    parameter real amplitude = 0.4; //sine amplitude
	parameter real offset = 0.4; //offset voltage

    // Phase noise profile
    parameter real phase_noise_offsets[5:0] = {10, 100, 1e3, 1e4, 1e5, 1e6}; // Offsets in Hz
    parameter real phase_noise_dBc[5:0] = {-63, -93, -118, -135, -136, -136}; // dBc/Hz

    // Harmonics and sub-harmonics
    parameter real harmonic_amplitudes_dBc = -25; // Harmonics < -25 dBc
    parameter real subharmonic_amplitude_dBc = -60; // Sub-harmonics < -60 dBc

    // PLL and spurious tones
    parameter real pll_amplitude_dBc = -60; // PLL & divider products < -60 dBc
    parameter real spur_amplitude_dBc = -80; // Spurious tones < -80 dBc

    // Internal signals
    real phase = 0.0;
    real phase_noise;
    real noise_contrib;
    real harmonic_amplitude, subharmonic_amplitude, pll_amplitude, spur_amplitude;
    genvar i, h;

    analog begin
	  // Time-step calculation
	  // Base phase update for center frequency
	  phase = phase + 2.0 * `M_PI * freq_center * $abstime;

	  // Add phase noise contributions
	  phase_noise = 0.0;

		for (i=0; i<6; i=i+1)
		begin
			noise_contrib = $rdist_normal(23, 0, 10**(phase_noise_dBc[i] / 20));
			phase_noise = phase_noise + noise_contrib * sin(2.0 * `M_PI * phase_noise_offsets[i] * $abstime);
		end
		phase = phase + phase_noise;

	  // Initialize output signal

	  // Add harmonics
		harmonic_amplitude = amplitude* (10**(harmonic_amplitudes_dBc / 20)); // Convert dBc to linear
	  for (h=2; h<=5; h=h+1)
		V(out) <+ harmonic_amplitude * sin(h * phase);

	  // Add sub-harmonics
	  subharmonic_amplitude = amplitude* (10**(subharmonic_amplitude_dBc / 20)); // Convert dBc to linear
	  V(out) <+ subharmonic_amplitude * sin(0.5 * phase); // Half-frequency sub-harmonic
	    V(out) <+ subharmonic_amplitude * sin(0.25 * phase); // Quarter-frequency sub-harmonic

	  // Add PLL & divider products
	  //pll_amplitude = amplitude * (10**(pll_amplitude_dBc / 20)); // Convert dBc to linear
	  //V(out) <+ pll_amplitude * sin(2.0 * `M_PI * (freq_center / 4) * $abstime); // Example product

	  // Add spurious tones
	  spur_amplitude = amplitude * (10**(spur_amplitude_dBc / 20)); // Convert dBc to linear
	  V(out) <+ spur_amplitude * sin(2.0 * `M_PI * (freq_center - 1e9) * $abstime); // Example spur
    end
endmodule

 

Dear Sheldon，  I use stability analysis. I think in the beginning of the buildup, it is linear.

Chang,

  Are you using stability analysis or periodic stability analysis?

                                                                        Sheldon

Hi , I have  a problem on simulation of xtal oscillator. When I simulatie a Santos xtal OSC, I use STB to get its gainmargin which I found it is -1.5dB.So it should not to oscillate, but I found it can oscillate corectly when I use transisent analysis.  Can anyone explain this descranpcy?

Thanks a lot!

Hi all,

I'm currently using a separate Calibre gui from Cadence, and learned from this vid(https://www.youtube.com/watch?v=oMZZ9q3f10A&list=PLP4ZmM6GPuePeV6zkmb0wVBm11xplE...) , that there's a way to merge those tools together.

An edaboard post( https://www.edaboard.com/threads/how-to-add-calibre-into-virtuoso.23011/) mentioned I need first to create a .cdsinit file.

But I'm unsure where I should create the file.

Anyways, does anyone know where I can find more information abt it?

Thanks a lot:)

smlogan wrote on Jun 8^th, 2023, 5:31pm:



I want to know in the above case, how "low frequency" will the vco PN contribute to the pll PN. if the pfd dead zone time window is 100ps, and in your case, fref=10M, divider ratio=10, fvco=100MHz, then, what is the frequency range of the vco phase noise will be the pll phase noise?

thanks