To solve the issue mentioned in the previous reply the variable "prev" was also "reseted" to 0.0.
Additionaly the freq is calculated only if "prev" is greater than 0.0.
With this modification I am getting the expected results. See picture below.

Again, thank you very much for your help. I see now how disabling the block implements what the @timer function was doing in veriloga.

Thank you very much for your answer Ken!

You are right when you say that the approach using

   always @(VCO_OUT) begin

will not work well on non-symmetric waveforms. This approach assumes a 50% duty cycle which is not necessarily the case.

Therefore I followed your suggestion of using the posedge.

I tried implementing your approach and it is working almost fine.

The real variable "freq" becomes 0.0 when we have a period longer than e.g. 40ns.

The only problem is that as soon as VCO_OUT goes high again the frequency will be re-calculated immediately with the values of variables "t" and "prev" because these values were not "reseted". See picture below.

In frac-N PLL, if I use dual-modulous divider as shown in the figure, what is the safe time window to update the divider ratio control word P<N:0>?

Intuitively the safe window is to update the p<n:0> when all mod0-modn signals are logic low. Not sure if this is correct and can assure the divider operates glitch-free.

Thanks,
Neo

Here is how I have implemented this idea in Verilog-AMS.
//determine frequency of output
Code:

always @(posedge out) begin
    t = $abstime;
    freq = 1.0/(t – prev);
    prev = t;
    disable oscDead;
end

// if no crossing for a while, assume oscillator is dead
always begin : oscDead
    #(100n) freq = 0;
end 

Notice that the first always block triggers on posedge out.  You don't have the posedge, so you are measuring the half-period rather than a full period.  You approach will not work well on non-symmetric waveforms.

-Ken

Yes thanks a lot. However, once the PSS is done, assuming I had not selected the option for producing the periodic op point into a file I guess the results are lost right?

Marios

I think that NF is usually independent of device gds. The reason is that both source noise and signal experience same gain. What we are after is to minimize noise added by device itself. This is done by increasing device gm.

In the same manner that adding another NMOS in parallel with the original NMOS increases gm by a factor of 2 (thus decreasing noise contribution by device), adding a PMOS on top of the NMOS inceases gm by a factor of two (assuming gm_p = gm_n). However it is usually achieved without consuming more power (assuming no extra headroom is required).

Marios

There is an option to write the periodic operation point into a file in the PSS analysis, and there must be an option to load this file in for PAC analysis. I've never tried it, but it should work. It is analogous to how the DC/AC pair would work.

I hope it helps. I can't check the exact option right now, and I thought you would appreciate such a vague answer, if it points you into the right direction.

Hello guys,

I have a question with regards to PSS and PAC. Assuming a PSS has just finished, can I somehow run a PAC without re-running PSS? And how would I do that?

Best regards
Marios

Please see attached picture.

Hello All,

there is a similar thread covering this, but using veriloga/verilogams: https://designers-guide.org/forum/YaBB.pl?num=1629723383

Now I would like to implement the same but using wreal only (or systemVerilog) i.e. I cannot use the @timer function.

If the clock doesn't toggle then the frequency should become zero after a duration that is longer than the period of the lowest frequency that is expected.

What is the best way to implement this?

I am using the code below as a starting point. Thank you very much!


// MEASURE ACTUAL DIGITAL FREQUENCY:
real fdig,tupd=0;  

// on leading clock edge
always @(VCO_OUT) begin
 //  compute F=1/period (Hz)
 if (tupd>0) fdig=1e9/(($realtime-tupd)*2);
 tupd = $realtime; //   and save edge time
end