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Dec 5th, 2019, 5:17pm
1  Analog Verification / Analog Performance Verification / Re: Noise options when simulating with Spectre and ADE-L
 on: Today at 4:17pm 
Started by vivkr | Post by sheldon
I believe you are referring to the ability to control which noise sources
contribute during transient noise analysis. This is provided as a tool for
debugging transient noise issues.

Since you enabled 1/f noise for a device, you turned off the other contributions
for that device. However, all the other devices are still contributing noise.

For example, you enabled M1 1/f noise, then the results will include the
1/f noise contribution for M1 and the all the other noise source for all the
other devices in the design.

You will need to turn the other noise sources off, if you only want to see
the noise from M1 1/f noise

2  Simulators / Circuit Simulators / Re: Noise floor in Spectrum
 on: Today at 4:11pm 
Started by Ali1990 | Post by sheldon
I have tried other experiments with low sideband windows and these produced similar results. Since the input source has very high dynamic
range, the noise floor of the FFT, ~ -300dB, see the PSS plot. The noise
floor is below the noise floor of the FFT is potentially below the level
of the windowing function.

3  Simulators / Circuit Simulators / Re: Noise floor in Spectrum
 on: Today at 4:08pm 
Started by Ali1990 | Post by sheldon
Example II, the whole spectrum

4  Simulators / Circuit Simulators / Re: Noise floor in Spectrum
 on: Today at 4:07pm 
Started by Ali1990 | Post by sheldon
Given the available data it is difficult to know for sure what the problem
is, however, I suspect that you are seeing the effect of the windowing
function on the data. If you look at the following two plots you will see
a similar pattern. The Spectrum is effected by the window close in to the
tone. However further out, where the window function is below the FFT
noise floor, the FFT noise floor becomes visible.

5  Design / Analog Design / Re: How to speed up RJ sim for DLL including Regulator
 on: Yesterday at 11:33pm 
Started by aks | Post by kumar.g
low_fre_of_interest is the lower limit of the PLL noise integration. Like you have mentioned in your post, to include the low frequency noise, you will have to simulate upto 1us. However simulating just the regulator as a standalone should speed up your simulation compared to simulating with the PLL.

6  Modeling / Semiconductor Devices / Re: Limits of frequency for device noise generation and BSIM models
 on: Yesterday at 9:33am 
Started by vivkr | Post by Geoffrey_Coram
Thermal noise is usually modeled as white noise, which extends to all frequencies.
Perhaps your question is whether this noise should be filtered out or at least not amplified by the transistor.

7  Modeling / Semiconductor Devices / Limits of frequency for device noise generation and BSIM models
 on: Yesterday at 5:32am 
Started by vivkr | Post by vivkr
Hello,

Is there any reason to expect that channel thermal noise might be generated beyond transistor fT?

What is the limit of frequency that one might reasonably expect to see noise contributions at, and are these adequately captured in BSIM models? I seem to be getting noise contributions from channel current well beyond (an order of magnitude) the device fT and I think this doesn't make a lot of sense.

Thanks,
Vivek

8  Design / Analog Design / Re: How to speed up RJ sim for DLL including Regulator
 on: Yesterday at 4:18am 
Started by aks | Post by aks
Thanks Kumar.. You mean noise at "low_freq_of_interest"  or spot noise at say 1MHz?
Actually I was thinking of using integrated noise over range of freq. of interest which covers (Lowest freq of interest to freqDLL/2) and use it as you mentioned.
But then the DLL must be simulated for long enough time to cover impact of the slow moving noise (pwl) spanning over lowest freq of interest (i.e lowest freq 1M Hz => 1usec!! ) which becomes very lengthy simulation and time consuming.

Thanks

9  Design / Analog Design / Re: How to speed up RJ sim for DLL including Regulator
 on: Dec 3rd, 2019, 5:07am 
Started by aks | Post by kumar.g
You can first simulate just the regulator and extract the noise of the regulated voltage for a time of say 1/low_freq_of_interest. Then use this noise in DC source of the DLL test bench as a piece-wise-linear model.

10  Design / Analog Design / Re: Ring Oscillator Pre vs. Post Layout Frequency Shift
 on: Dec 3rd, 2019, 4:59am 
Started by melvin1109 | Post by kumar.g
The layout parasitics can not increase the RC time constant by 300% unless it is done in a complete amateurish way. You can search it on the web and you will find general guidelines to do a proper layout.

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