when the spectre fx run above 10h， the tools will display the following error log:
Internal error found in spectre at time = 4.12725 ms during Transient Analysis `tran'.
   FATAL (SPECTRE-18): Segmentation fault.
       Encountered a critical error during simulation. Submit a Service Request via Cadence Online Support, including the netlist, the log files, the behavioral model files, and any other information that can help identify the problem
       Encountered a critical error during simulation. Submit a Service Request via Cadence Online Support, including the netlist, the log files, the behavioral model files, and any other information that can help identify the problem
****ASSERTION STACK****
       0x7954dac
       0x9b297c
       0x9b34b6
       0x2b2810a96630
       0x2b28133c9fc3
       0x86591ad
       0x86597c0
       0x863c34d
       0x862c094
       0x85754f5
       0x85755f9
       0x857596f
       0x857fba9
       0x8582946
       0x2b2810a8eea5
       0x2b28133e096d

****LIBRARIES****
/edatools/cadence/spectre_test/spectre231/tools/spectre/bin/64bit/spectre [0x400000]
       /lib64/libpthread.so.0 [0x2b2810a87000]
       /lib64/libc.so.6 [0x2b28132e2000]

In Virtuoso 23.1 ISR14 and Spectre 23.1 ISR13, the results YG, YL, ZG, and ZL have been added to the stb analysis (see page 9 of https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1OPP000001RAnV2AW). As the official documentation on these quantities is a bit incomplete from my point of view (I have asked for improvements in Case 46927677), here is a simple example that hopefully shows all the details.

Important points to note:

• The PLUS pin of the iprobe is associated with ZL and YL; the MINUS pin of the iprobe is associated with ZG and YG.
• ZL and ZG are determined by the insertion of a voltage source (same current on both sides).
• YL and YG are determined by the insertion of a current source (same voltage on both sides).
• ZL and ZG correspond to the impedances provided by the sprobe, but don't suffer from the numerical problems of the sprobe when very low impedances are connected (I had CCR 2029190 filed on this problem 7 years ago).

Quote:

Fundamentally a complete verification flow includes both performance and functional verification.  Knowing how much to do is something that comes from experience.  Of course you should verify all required specs and all required functionality.  This later requirement means that you must exercise all modes and settings.  Most analog circuits these days do not contain significant state (digital state machines), so functional verification largely requires exercising all digital wires that connect to the circuit.

Quote:

Analog and mixed-signal verification are the same thing.  Virtually all analog circuits on modern analog system ICs have digital controls.  So you can say you are verifying an analog circuit or you can say you are verifying a mixed-signal circuit.  It is the same thing.  I am a proponent of using the term: analog verification.

I have been focused on analog verification for many years, and I have never used nor considered using UVM-MS.  When I looked at it my conclusion was that it was an attempt to apply digital verification techniques to analog circuits, and it never seemed like a good fit to me.  I got what I needed from plain Verilog-AMS, and I found it was a better fit.

UVM-MS and Verilog-AMS are used mainly for functional verification.  Both employ transient simulation.

The small signal analyses, by their nature, are used for performance verification.

Verilog-AMS can also be used for performance verification but it tends to be used for different performance metrics.  The small signal analyses are used to measure performance metrics associated with small-signals such as bandwidth, stability, noise, etc.  Transient analysis base simulation techniques are more suited metrics associated with large signals and are used to extract inherently nonlinear behavior such as distortion or locking behavior in PLLs.

Quote:


The way I distinguish performance and function is as follows:

• The performance of a circuit varies with small changes in parameter values.  The circuit fails a performance check if the performance does not satisfy a minimum requirement.  Given the nature of performance, it is conceivable that small changes to parameters could cause the performance check to pass.
• Circuit function is not affected by small changes in parameter values.  For example if a wire is broken so that the signal cannot pass through the circuit, that is a functional failure.  Small changes in parameter values in the circuit cannot fix this issue.

Examples of functional failures:

• an inverted enable
• a logic error
• a swapped bus
• a polarity error
• a loop of dependencies (bias block depends on LDO, but LDO depends on bias block)
• etc.

Example of performance failures:

• insufficient gain
• insufficient bandwidth]
• too much noise
• etc.

-Ken

Hi everyone,

I’m currently working on analog circuit design and verification and have run into a few confusing points. I’d really appreciate it if anyone with experience could share their insights! Here are my questions:

1. Most specs for analog circuits focus on performance. When we design circuits like LDOs, opamps, or PLLs, our core goal is essentially to create circuits with sufficient performance. If a circuit fails to meet the predefined performance metrics, it’s considered unqualified in the system. Conversely, a circuit that meets performance requirements will also fulfill its intended system functions. This makes me wonder: How do we distinguish between "performance" and "function" for analog circuits?

2. Is UVM-MS the ultimate solution for analog and mixed-signal verification? In a way, simulations like AC, DC, stb, and noise analysis all represent different perspectives on transient simulations. However, UVM-MS focuses more heavily on tran simulations. This leads me to ask: Can the UVM-MS framework replace traditional analyses like AC, STB, or PSS  simulations? When I use UVM-MS, I keep questioning whether it covers everything needed. I also want to understand: What’s the fundamental difference between relying on UVM-MS versus using AC/PSS/STB simulations?

3. For analog circuits in general, how do we build a complete verification flow? And more practically, how can we prove that a designed analog circuit is truly qualified? This is another key confusion I haven’t been able to resolve.

Thanks in advance for any advice or discussions—your input would be a huge help!

Best Regards
Lewis

This Topic has been moved to Analog Functional Verification by Ken Kundert.

hi，all！
To analyze the pole-zero effects, I also attempted to perform a PZ simulation (Pole-Zero analysis), the results of which are attached.

Hi all, I have encountered some challenging issues:

(1) When performing STB simulation analysis on an OPA with a feedback loop, I observed: When VDD <5V, the phase curve appears normal. However, when VDD >5V, the low-frequency phase approaches 0°. The circuit schematic and simulation results are attached.

It should be noted that the differential pair in the circuit is not operating in the saturation region (to minimize the minimum operating voltage). This circuit was originally designed to operate at VDD <5V. I attempted to modify its process  to enable operation at higher voltages (e.g., 7V).

(2) For a chopper-stabilized operational amplifier with a feedback loop consisting of multiple switched capacitor networks (selecting different capacitor groups at different time intervals), I encountered similar low-frequency phase approaching 0° phenomena when performing stability analysis using PSS+PSTB simulations.

As a newcomer to this field, I'm unable to determine the root causes or solutions. I sincerely hope to receive valuable suggestions from experienced colleagues.

hi, all
I simulate with spectre x, now, I have done the phase noise simulation with post rcc extraction netlist. but in the noise summary, the parasitic r is shown with G1bI_RCNet_xx， I have checked the "write RCNet box" in noise summary, but there is no description of the relationship between "G1bI_RCNet_xx" and the extracted rcc netlist, how can I know which net  "G1bI_RCNet_xx" corresponds to ??

thanks