Hello Everyone,
I am using the code below for VCO, and it is pretty standard and straightforward. I want to make sure that the noise transfer function from control voltage to phase noise is correct, as I am going to use it in my PLL. Now, when I put a purely thermal noise using a resistor on the control voltage, the output phase noise slope is -40dB/dec using PSS and Pnoise!!!!  Just to clarify, I do not want to model VCO PN itself but I wanna make sure that the transfer function of noise from its control voltage to output is correct.
I would appreciate any comment if you see it as helping. I am attaching both schematic and simulation results below.


module vco_va(vin, voutp, voutn);
input vin;
output voutp , voutn;
electrical vin, voutp, voutn;
parameter real amp = 0.5;
parameter real center_freq = 20G;
parameter real vco_gain = 1G;
parameter integer steps_per_period = 32;
parameter real DC_val = 1;


  real  phase;
  real inst_freq ;


  analog begin


           
            inst_freq = center_freq + vco_gain * (V(vin)-1.25);
           
           phase = idtmod(inst_freq, 0,1);


     $bound_step (1.0 / (steps_per_period*inst_freq));
           
           V(voutp) <+ amp * sin (2*`M_PI*phase) + DC_val;
           V(voutn) <+ -1*amp * sin (2*`M_PI*phase) + DC_val;
  end
endmodule

Hey ,I am new to the field and interested in the RF field and would love to take the first step

Hi,
1) I simulated the phase noise of LC VCO at 5GHz in cadence and integrated from fl=10Hz to fh= 2.5GHz to get jitter as follows
Jc=1/(2*pi*fc)sqrt(2*integ(10^PN/10) from fl to fh)

I find it to be 960ps!!
I tried to compare with time average Jc and interated from fl=10Hz to fh=2.5GHz using cadence direct plot and I can see only 6.7f

How do I get it from phase noise skirt?

2) Also, since phase noise theoretically is boundless and becomes infinite at 0Hz, intgerating it will also give boundless value. Is it equivalent to saying that accumulation jitter is also boundless?

I tested current force, voltage measure with same sample and probe, tester, but the results (voltage level) were different when compliance level changed. Do you have similar experience or can you give me any advice regarding this?
For example,

Force [I] || Comp [V] || Measure [V]
-100 uA  || -1.5V       ||  -1.5V
-100 uA  || -3V          ||  -1.2V

Don't you need a contact layer to connect the resistor to M1?

The DRC violation is for the poly segment connecting PMOS and NMOS gates. You can add/ extend P+ and N+ implant layers between the MOS devices, such that they are touching. This will cover all poly layers by either P+ or N+ implant.

Can you clarify what is the GCD layer, please? Generally dummy fill rule deck will generate all necessary fill layers for a given design.

The "source could not be read" error means the source netlist is not available for the LVS run. Please check the netlist file path.

:D Calculation the output resistance of each stage using definition. Especially for the ac source connected @ the output.

Hey, I have a question about the sweep points limit in Cadence ADE Assembler. I've noticed that, unlike ADE XL, ADE Assembler seems to have a cap of around 1e6 points. Back in the ADE XL days, I could optimize without this kind of restriction. Does anyone know why the limit's been introduced with the update to ADE Assembler and Explorer? More importantly, is there a way to push this limit higher for extensive sweeps