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Sep 18th, 2020, 1:21am
1  Simulators / Circuit Simulators / Re: Switched capacitor stb simulation issue
 on: Sep 14th, 2020, 10:33pm 
Started by iVenky | Post by Ken Kundert
No, see that is the rub. You cannot simulate a ΔΣ modulator because it does not have a periodic operating point.

In other words, you want to simulate the circuit within a representative environment so your results are representative, but sometimes you cannot. This is why you added the large resistors around the integrator. Those resistors are not represenative, but you need to something so the circuit has  a fixed operating point. The trick is to come up with a test circuit that allows you to simulate what you need while also being representative of the actual circuit.

Unfortunately, I have no recommendation.

-Ken

2  Simulators / Circuit Simulators / Re: Switched capacitor stb simulation issue
 on: Sep 14th, 2020, 11:10am 
Started by iVenky | Post by iVenky
Hi Ken,

Thanks for the reply. You mean like if this is used in an SDM, then I should include the entire SDM (or an equivalent model) so that it converges? Is that what you mean?

3  Simulators / Circuit Simulators / how to get SNR for delta-sigma DAC
 on: Sep 12th, 2020, 9:47pm 
Started by sycamore | Post by sycamore
Hello everyone! Lately I have simulated fully differential OTA with chopper stablization circuits. I need to get SNR of output waveforms. The first methd of getting SNR is that I simulate it by tran noise simulation and I can get the output waveforms, after FFT transforming, I can read the result of SNR. The second way is PSS simulation. And I can get the spectrum of noise then by some mathematical calculation I can get the SNR. But these two ways attain two different results. I don't know which way of simulation is accurate. I hope that I can get yours answers. Thank you!

4  Simulators / Circuit Simulators / Re: Switched capacitor stb simulation issue
 on: Sep 12th, 2020, 3:18am 
Started by iVenky | Post by Ken Kundert
An AC analysis is 'frozen' in this situation because it is applied at a fixed operating point, meaning that the clocks are frozen.

Yes, open loop integrators are always problematic, and are never used in practice. It is always better to make your test circuits as close to the real circuit as possible. Some times that is hard with clocked integrators because PSS analysis requires the circuit be periodic, but when you include the rest of the circuit you end up with a system that is not periodic.  None the less, you have to try to get as close to the real application as you can.

-Ken

5  Simulators / Circuit Simulators / Re: Switched capacitor stb simulation issue
 on: Sep 11th, 2020, 6:33pm 
Started by iVenky | Post by iVenky
Hi Ken,

Thanks so much for your reply. I appreciate your time. What's "frozen" ac analysis?

Also, I am not sure of pss converging for an integrator when I try to do pstb analysis. I have seen documents online for running pstb for switched capacitor amplifier but not for a switched capacitor integrator.

6  Simulators / Circuit Simulators / Re: Switched capacitor stb simulation issue
 on: Sep 11th, 2020, 4:12pm 
Started by iVenky | Post by Ken Kundert
You should use pstb analysis as it is the most realistic.  You can use a 'frozen' AC analysis for an extra check if you like to give yourself more confidence, but it should not be at the expense of a pstb analysis. With the pstb analysis you are testing your circuit in the same way it will be used, whereas trying to us AC analysis creates an artificial situation that does not really match the way the circuit works.

It is also a good idea to run simple transient.  Normal stb analysis does not cover extreme situations, such as when the circuit is seeing a rapid step on its input which would cause the circuit to go into slew-rate limiting. Slew rate limiting is often a source of large-signal instability. I don't think this particular circuit is really subject to large-signal stability issues, but it is always good to check.  To check large-signal stability you apply large steps that change very rapidly. It is good to also set maxstep to a small value. Then look for ringing that is unexpected or excessive.

-Ken

7  Simulators / Circuit Simulators / Re: Switched capacitor stb simulation issue
 on: Sep 8th, 2020, 11:50pm 
Started by iVenky | Post by iVenky
Sorry, if I wasn't clear before.

First, I just did stb analysis by placing a 1G feedback resistance to make the DC converge.

Second, I ran transient simulation and then ran stb (By enabling prevoppoint in the STATE-FILE PARAMETERS options window). This runs stb using the small signal parameters available at the tran end time I guess, right?

What do you think is a good way to simulate stb for a switched capacitor network like the one shown above? I tried pstb but I think pstb works well when phi1 and phi2 circuits are same (like in chopping or switched cap cmfb), right? Does it work well with the circuit shown above? Also, it's an integrator (not an amplifier) so obtaining periodic operating point is not that straightforward.

Thank you very much for your reply!


8  Simulators / Circuit Simulators / Re: Switched capacitor stb simulation issue
 on: Sep 8th, 2020, 7:55pm 
Started by iVenky | Post by Ken Kundert
There is not really enough information to go on.  Two issues that you should resolve are:
Quote:
ac and tran stb
Not sure what what that means. If you are using AC analysis, you should stop. To measure loop gain and stability you should be using the stb analysis.  As far as I know there is no tran stb analysis, so you should describe what you mean by that.

Quote:
the frequency spectrum @ low frequencies (<10kHz) has weird issues
That is just to vague to allow me to offer any help.

And what are the two curves in the graph.

-Ken

9  Simulators / Circuit Simulators / Re: Switched capacitor stb simulation issue
 on: Sep 8th, 2020, 6:01pm 
Started by iVenky | Post by iVenky
Hi,

Any suggestions would be greatly appreciated.


Thanks Smiley

10  Design / RF Design / How to ensure the pll loop stability with VCO gain variation?
 on: Sep 5th, 2020, 5:45am 
Started by tulip | Post by tulip
I designed a PLL, the VCO's control voltage Vtune is in the range of  0.7V~2.5V, the VCO(ring VCO) can oscillate from 10M to 1.2G, the target frequency of VCO is 500M, when the PLL locks, the Vtune  is about 1.2V.
The problem is: the VCO gain at Vtune =0.7 or 2.5 (two ends of the tuning range) is very low, especially at Vtune =0.5, the VCO gain is 100M/V, while at Vtune=1.2, the VCO gain is 680M/V, consider about process corner and temperature variations, the VCO gain variation is much bigger.

I designed the loop filter, which can ensure stability when VCO gain is among 300M/V to 1.4G/V, but at low end of the VCO tuning range(Vtune=0.7) , the VCO gain is 100M/V, the pLL is not stable.

At the PLL taget frequency, the VCO tune voltage is between 1~ 1.2V, far away from the low end of the VCO tuning range.

My question is : Will my PLL work properly? when vtune is 0.5V(at this vtune voltage,  the PLL loop can be unstble), can it converge to the target voltage of 1.2V?

Thank you.

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