Hello,

I am doing Behavioral Modelling of PLL using Verilog-ams. I have use Laplace function for loop filter. My error signal (output of the filter) which is the input of VCO is going beyond VDD. How can I keep it below or equal to VDD.

Below is the code
//"verilogams"

`include "constants.vams"
`include "disciplines.vams"

module analog_lapalce_filter (in,out);
parameter real R=1K;
parameter real C1=1p;
parameter real C2=1p;
input in;
output out;
electrical in,out;
analog
begin
V(out)<+ laplace_nd( V(in), { R*C1,0},{R*C1*C2,C1+C2,0} );
end
endmodule

I have also attached the loop_filter which I am using.

Thank you for your help in advance!

Thank you again for your very helpful answers Ken!

Regarding t0:
it is working fine as the code is written above but I will follow your advice and then test it when I change the frequency from e.g. f1 to f2.
For this I am also using the VCO model that I found here.

Regarding Charge Pump:
Yes, it is a Charge Pump that is used to raise a voltage above the supply.
I found a very helpful paper that I using as a reference and adjusting it accordingly.
It also uses an ideal transformer: https://www.mdpi.com/2079-9292/9/6/998.

I am only modeling the Charge Pump stage, CPmodel in the paper above.
It is working pretty fine stand-alone where I enter the frequency as a parameter.

The problem is that I have to put it then in a regulated loop which sends clocks, that's why I had to adjust the model to track the frequency of the input clocks to make the model frequency dependent.
If I use the frequency as a parameter the Chargepump will increase the voltage even when there are no input clocks.

Regarding the update of the frequency measurement:
The picture below shows the initial simulation that I had (regulated loop with several instances of the N-Stage).
I defined one Stage stand-alone to have an output voltage of ~4.7V . If I run one stage of the schematic stand-alone I also reach ~4.7V.
As you can see the regulated loop schematic simulation goes to ~3.3V, with the model it goes to ~4.7V.
The picture show the initial version where the frequency was not updated to 0.
I run another simulation with the updated frequency measurement, but then I had to add time_out_delay=6u because of Fmin, but then freq updates only after 6us which is too long and the output voltage increased again up to ~4.7V.

Question:
So, now even when the frequency measurement goes to zero the output voltage continues increasing up to ~4.7V.
Any ideas about what could be the reason?

I don't think you put the line that sets t0 in the right place. It should go in the first event block after period is computed.

There are many kinds of charge pumps, and peoples needs differ greatly, so it is hard to recommend a modeling approach.  If the charge pump is meant for a PLL, then I use a pulsed current source output (be sure to pass the output current through a transition function to control the edges).  For a charge pump that is used to raise a voltage above the supply, I tend to use an ideal transformer. Doing so is very efficient as the clock is not included.

As for your approach, it seems fine.  Current pulses also seems fine.  Be sure to use a transition function in either case.

-Ken

One additional picture that could not be added:

Thank you very much Ken,
it is working fine.
A line of code was missing: to update t0=t.
The code that I am simulatinng now looks like this:

     t = last_crossing(V(clkA_in) - thresh, +1);
     @(cross(V(clkA_in) - thresh, +1)) begin                  
           period = t - t0;
           freq = 1/period;
           t_reset = t + time_out_delay;  
     end
     t0 = t;
     @(timer(t_reset)) begin      
           freq = 0.0;
     end      
     
In the screenshots shown below I defined:

parameter real time_out_delay=11u;

and we see that it fits.

My idea is to model a Voltage Multiplier (e.g. Charge Pump).
The frequency was constant (last measured value) even when there was no input clock and this made the output voltage increase further.
Now that freq goes to zero it should be ok. I need to test it.
I hope that the additional delay time_out_delay=1/Fmin doesn't affect much and the output voltage does't increase too much.

One more question:
Is my approach of modeling a Charge Pump with a Voltage source in series with a switch, a Resistance and a Capacitor a good idea or would you suggest another approach e.g. current pulses instead of a voltage source?
The output voltage is the node between the resistor and the capacitor. The switch is controlled by the clock. There is only one clock, it is not like in a PLL where we have a reference and a feedback clock.

Add a time out.  Choose a time out duration that is longer than the period of the lowest frequency that is expected.  Every time you compute a frequency, also update the time of reset.  When you reach the reset time, set the frequency to 0.  If the input clock is operating, you should never reach t_reset because on every cycle of the lock it will be pushed out of reach.  Something like this:

Code:

t = last_crossing(V(clkA_in3m) - thresh, +1);
@(cross(V(clkA_in3m) - thresh, +1)) begin
    period = t - t0;
    freq = 1/period;
    t_reset = t + time_out_delay;
end
@timer(t_reset)
    freq = 0; 

Hello All,

I am trying to create a model which is dependent on the frequency of the input signal clkA_in3m.

I am using the model "Frequency measurements (dg-vams4-8)." as a reference:

https://designers-guide.org/verilog-ams/index.html

The relevant part of the code is below.

     //****** Frequency Measurement **********
     t = last_crossing(V(clkA_in3m) - thresh, +1);
     @(cross(V(clkA_in3m) - thresh, +1)) begin                  
         if (timing) begin
                 period            = t - t0;
                 freq            = 1/period;
                 Req2 = k/freq;                                                      
         end
           t0      = t;
               timing      = 1;  
     end

The frequency measurement works pretty well. I then use "freq" to adjust the value of another variable, let's say "Req2".
The problem that I have if that if the clock signal remains constant the variable "freq" keeps showing the same last value which is wrong and then my variable "Req2" remains constant which is also wrong.
I know that the reason is because there are no clocks. How can I make the "freq" to update to a predefined value, let's say 0.1 (Hz) in such a scenario?
Thank you very much for your help.  :)

Dear All-
I haven't seen any bandgap design with npn devices, through they are available in the kit? At least in TSMC i have seen both npn and pnp but every one (including me) designed with pnp itself? Their Beta values are very similar even. Can any one please share your experience or please point me a reference.

Thanks,
Raj.

This question has been answered by Andrew Beckett at https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/48795...

pnoise2