This paper may be helpful.

C. Galup-Montoro, M. C. Schneider, and I. J. Loss, ‘Series-parallel association of FET’s for high gain and high frequency applications’, IEEE Journal of Solid-State Circuits, vol. 29, no. 9, pp. 1094–1101, 1994.

Hi, Is there a way to account for high resistivity substrate in EM simulation software? I am designing an inductor in a CMOS process and using high resistivity substrate to get high Q factor. I have momentum and emx software.

Also interested in this topic. A drop here a reference I found helpful

D. Lee and J. Han, «Design Techniques for Area-efficient Two-Stacked Current Sources in Nanometer CMOS Technology», 18th International SoC Design Conference (ISOCC), 2021. doi: 10.1109/ISOCC53507.2021.9613881.

Did you find the jitter value from your Verilog-A / matlab script was matched with the guide (9.8 ps?).

You can use the semi-autonomous hb/hbnoise analysis, see https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nTyrEAE, https://support.cadence.com/apex/techpubDocViewerPage?path=spectreRFTheory/spect... and https://support.cadence.com/apex/techpubDocViewerPage?path=spectreRFinExplorer/s....

We are trying to run a phase noise simulation in SpectreRF (autonomous oscillator) with some modulation applied (repeatable pattern).
Any hints and tips ?
Thank you.

Hi, I'm trying to find the best practices for sweeping temperature for some subcircuits of my design while keeping other sections at another constant level. What is the best way of doing this? **EDIT: Forgot to add, I'm trying to do this in spectre, version should be latest, but I will check again tomorrow.

More detailed problem definition: I have a positive temp co current generator that feeds a current into an oscillator that has a negative temp co characteristic so the current generator compensates for the temp variation to a degree. I would like to simulate the temp co effects of these subcircuits on the frequency without separating them or modifying the schematic.

My naive solution that I don't like: I can easily separate these circuits and buffer them or just feed sim output from one to the other. I don't want to do this. I don't have a reason, I just don't like it  ;D . It's not elegant.

Several related solutions I could find from Cadence forums: I've found the following solutions, but these are pretty old. I would like to check whether there are better ways available in newer versions.

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/25211...
https://community.cadence.com/cadence_technology_forums/f/rf-design/43557/indivi...
I do not like the solution above, because I would have to define it for a lot of devices which is tedious and requires actual parameter changes in the circuit.

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/26780...
I think this solution is closer to what I want but it's a very old response and personally I have a bit of a dislike for MTS stuff (not a rational dislike, I just distrust stuff I don't use as often and my past experience with MTS was problematic in a big project).

I would appreciate any advice on how to do it, or where to look for more info, or any keywords that would put point me in the right direction.

Thank you.

Dear subtr,
Do you still have an interest in your question? If so, I can share an Excel workbook that you can use to place your control voltage noise data (noise versus frequency) and it will plot the resulting output phase noise given the Kvco.

Shawn

Hi Polyam,

usually PDK document contains a plot of Vth mismatch voltage vs. 1/sqrt(WL), can we find this constant from the plot?.

Thanks.

A PGA is required for a high precision DC signal sensing DSM ADC, with function of providing 1~128 signal gain, rail-to-rail input/output, buffering the ADC's SC sampling circuits. Other requirements are also critical: high input impendace, low noise/aliasing, low offset, low power, low INL.

There are generally 2 kinds of strcuture:
1) Resitive Feedback using two OPAs, Buffers are required to driving S/H stage.
2) Capacitive coupled PGA using 1 OPA, input precharge buffers are required to provide high input impendance.

Main challenges:
1) Driving capacibility is conflict with low alasing, anti-aliasing filter is requried before ADC S/H stage, but this will degrade the settling.
2) Varieties of dynamic techniques are used to improve settling without bringing noise problem. e.g. precharge, dynamic filter. BUT the switch's glitch become another serious problem.
3) Even I have solved all problems listed below, the power consumption is relatively high compared with industry benchmark.

I read many IA's papers (Huijsing, e.t.), but these IAs are usually designed for monolithic chip, usually a very large decoupling cap is conencted at the output.

Could anyone help point out any mistake of my understanding above? or provide any inspiration, materials about integrated PGA? Thank you very much!