It would have been nice to share to solution for others...

no dnl/inl simulation for sd adc

We decided to create a useful and productive tool-flow from available free/open-source tools. The first result of this work is now called RevEDA and includes Glade Schematic/Layout Editors including Gemini DRC/LVS and Xyce circuit simulator as well as RevEDA simulation GUI. A short video showcasing its status was uploaded to Youtube a week ago.

I thought it might be interesting for some members. If it is,  please contact me and I will try to answer your questions.

https://youtu.be/oOkTR9Fmiqw

Murat Eskiyerli

Long extraction time is a typical problem with parasitic extraction.

If your design is large in size, well, it's extraction will take time.

I would suggest to make sure there are no issues with the extraction setup / flow. Are you the first to use this flow, or are there other designers in your organization, who use it? What about their extraction time - is it too long, or OK?
Was extraction setup prepared by a knowledgeable person?

There are a number of settings or tricks that you can use to speed up the extraction.
For example, you can set Cmin and Rmin values - so that any capacitance or resistance below that will be ignored.
But beware of possible accuracy loss.
Also, you can extract in RC-decoupled mode, where all coupling capacitances are redirected to ground.

Do you need to extract power nets? These are huge things, and may take the major portion of the extraction time. Often, analog designers do not extract power nets, i.e. power nets are treated as ideal nodes.

There are a bunch of other things that you can or should check, or tricks that you can use, to speed up the extraction.

Of course, if your vendor (Mentor in this case) provides a good support, you can ask them to help.

For A GFSK demodulator for low-IF Bluetooth receiver , how does the shape-keeping circuit in figure 4(c) works ?

Besides, why need the NOR gate before the input to the shape-keeping circuit ?

Why if R3 is changed to 50 ohm, then the whole circuit cannot simulate at all ?  

How do you come up with your first rough estimate for how long it takes to design a circuit, its area, and current consumption?
In particular, say you had to add a high pass filter (to boost high frequencies) to a SERDES receiver, that wasn’t already there.  Just a hand-waving approximation of how many weeks it would take to design, verify, layout, post layout verify, and get first samples from the foundry. How much current it would draw, and how big it would be.  Say, for 45 nm.
Nobody’s going to hire you or me to do this.  Just an approximation.
You’re not committing to any accuracy here.  I appreciate it.
Thanks,
Bob P.

I have to delay a digital pulse by 30ns with an accuracy of ~1ps. Can this be achieved using the inverter chain delay line? If not, please suggest a topology. I couldn't find much literature on this.

I am using TSMC 65nm process.

I see. Thanks! I wish there was a way to find the location of poles and zeros approximately with stb analysis if I input an estimate of number of poles and zeros in the system.

I don't think so. Spectre also has a pz analysis, but I have never used it.

Is it fundamentally possible to find poles and zeros in stb analysis?