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Feb 26th, 2024, 3:55am
1  Design / RF Design / Integrate phase noise curve and compare with Jc (period jitter)
 on: Feb 10th, 2024, 8:32pm 
Started by vlsi_design | Post by vlsi_design
Hi,
1) I simulated the phase noise of LC VCO at 5GHz in cadence and integrated from fl=10Hz to fh= 2.5GHz to get jitter as follows
Jc=1/(2*pi*fc)sqrt(2*integ(10^PN/10) from fl to fh)

I find it to be 960ps!!
I tried to compare with time average Jc and interated from fl=10Hz to fh=2.5GHz using cadence direct plot and I can see only 6.7f

How do I get it from phase noise skirt?

2) Also, since phase noise theoretically is boundless and becomes infinite at 0Hz, intgerating it will also give boundless value. Is it equivalent to saying that accumulation jitter is also boundless?

2  Measurements / Other Measurements / Different result with same sample using probe and power supply
 on: Feb 1st, 2024, 12:10am 
Started by j828 | Post by j828
I tested current force, voltage measure with same sample and probe, tester, but the results (voltage level) were different when compliance level changed. Do you have similar experience or can you give me any advice regarding this?
For example,

Force [I] || Comp [V] || Measure [V]
-100 uA  || -1.5V       ||  -1.5V
-100 uA  || -3V          ||  -1.2V

3  Other CAD Tools / Physical Verification, Extraction and Analysis / Re: Calibre, LVS, new layer
 on: Jan 26th, 2024, 8:36am 
Started by balshoy | Post by ajithkv
Don't you need a contact layer to connect the resistor to M1?

4  Other CAD Tools / Physical Verification, Extraction and Analysis / Re: POLY1 must be covered by N+ or P+ implant layer @Umc40lp using Calibre
 on: Jan 26th, 2024, 8:16am 
Started by Ramakrishna RSSM | Post by ajithkv
The DRC violation is for the poly segment connecting PMOS and NMOS gates. You can add/ extend P+ and N+ implant layers between the MOS devices, such that they are touching. This will cover all poly layers by either P+ or N+ implant.

5  Other CAD Tools / Physical Verification, Extraction and Analysis / Re: GCD fill layer in 28nm technology
 on: Jan 26th, 2024, 8:10am 
Started by vlsi_design | Post by ajithkv
Can you clarify what is the GCD layer, please? Generally dummy fill rule deck will generate all necessary fill layers for a given design.

6  Other CAD Tools / Physical Verification, Extraction and Analysis / Re: Black boxing in calibre for IO cells
 on: Jan 26th, 2024, 8:06am 
Started by vlsi_design | Post by ajithkv
The "source could not be read" error means the source netlist is not available for the LVS run. Please check the netlist file path.

7  Design / Analog Design / Re: ring oscillator
 on: Jan 23rd, 2024, 5:25pm 
Started by theICdesigner | Post by ICDESIGNKING
:D Calculation the output resistance of each stage using definition. Especially for the ac source connected @ the output.

8  Simulators / Circuit Simulators / ADE Assembler Sweep Points Limit Compared to ADE XL
 on: Jan 17th, 2024, 1:59am 
Started by Jan_Martin_1043 | Post by Jan_Martin_1043
Hey, I have a question about the sweep points limit in Cadence ADE Assembler. I've noticed that, unlike ADE XL, ADE Assembler seems to have a cap of around 1e6 points. Back in the ADE XL days, I could optimize without this kind of restriction. Does anyone know why the limit's been introduced with the update to ADE Assembler and Explorer? More importantly, is there a way to push this limit higher for extensive sweeps

9  Simulators / System Simulators / how to design new coupler block to AWR?
 on: Jan 2nd, 2024, 6:24pm 
Started by EDA_chandler | Post by EDA_chandler
HI, EVERYONE. I want to use the whole ports of a coupler including coupled and isolated ports, as shown in figure. And All the ports of a coupler can be input port and output port. However, the coupler block from AWR has predefined input ports and output ports, for instance, coupled port is defined as a output port not a input port. When the coupled port is used as a input port, there will be a error. So i wanna find another way to achieve below network.


10  Analog Verification / Analog Performance Verification / Re: Modular Bench for characterizing OTA
 on: Dec 8th, 2023, 9:30pm 
Started by avlsi | Post by avlsi
The image posted here is a representation of the analysis and in a real bench, its a single source of each type and both DC and AC are part of the same. XF is interesting option.

Can common mode gain be measured with this configuration, or is a different setup required?

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