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Jan 23rd, 2022, 11:16am
1  Simulators / Circuit Simulators / Re: Cystal osc which satisfies start up condition cannot sustain oscillation
 on: Yesterday at 5:47am 
Started by unaffected | Post by unaffected
1. In the stb plot of crystal osc with small load cap, the lowest phase is -15 deg.
2. In the stb plot of crystal osc with 17pf cap at eash crystal node, the lowest phase is -53 deg.

As far as I'm concerned,in 1, the lowest phase -15 deg do not provide enough margin,perhaps this is the reason the crystal osc can not sustain oscillation.

I am not sure if my explanation is correct, any comments and suggestion are always welcome.

2  Simulators / Circuit Simulators / Re: Cystal osc which satisfies start up condition cannot sustain oscillation
 on: Yesterday at 5:32am 
Started by unaffected | Post by unaffected
This is the stb plot of cystal osc with 17pF capacitor at each node

3  Simulators / Circuit Simulators / Re: Cystal osc which satisfies start up condition cannot sustain oscillation
 on: Yesterday at 5:29am 
Started by unaffected | Post by unaffected
This is the stb plot of cystal osc with 6pF capacitor at each node

4  Simulators / Circuit Simulators / Re: Cystal osc which satisfies start up condition cannot sustain oscillation
 on: Yesterday at 5:27am 
Started by unaffected | Post by unaffected
The data sheet of crystal says the CL=9pF, in former simulation, I add 6pF capacitor to each crystal node(CL=3pF) ,  and the cystal osc can not sustain oscilation. After I changed the  cap at eash cystal node to 17pF, the cystal oscillate oscillate  steadily.

5  Modeling / Behavioral Models / Re: Minor glitches in nonlinear magnetics paper
 on: Jan 15th, 2022, 11:20pm 
Started by Geoffrey_Coram | Post by Ken Kundert
The first core and winding models in Spectre pre-dated Verilog-A, and I think they were purely linear.  When Mark joined the team we added the nonlinear core model in Spectre and created Verilog-A version of all the magnetic models and wrote the paper at roughly the same time. At least that is the way I remember it, but that was a long time ago.  Anyway, all that probably suggests that the units you found in the Spectre documentation are probably the right ones.

-Ken

6  Modeling / Behavioral Models / Re: Minor glitches in nonlinear magnetics paper
 on: Jan 15th, 2022, 11:12pm 
Started by Geoffrey_Coram | Post by Ken Kundert
Indeed.  That is very sloppy. Sorry about that.  The funny thing is that these days I am kind of a fanatic about units.

It would probably be pretty easy to figure out what the units are for the linear components.  But the nonlinear core model has a different heritage.  It would not surprise me if the units between the two did not agree.  The nonlinear core model is based on the paper by Jiles and Atherton.  It was enhanced by Mark Williams during a Master's project.  I think Mark was pretty careful about make sure things agreed with the original paper. Perhaps you can find the units in that paper.

-Ken

7  Design / Mixed-Signal Design / Re: Verilog AMS sine generator
 on: Jan 15th, 2022, 1:17pm 
Started by Praseetha Pn | Post by Praseetha Pn
Hi ken,
Thank you so much for the method and help.
I have used it in a similar way now, but modified as I need 4 signal sources.
Code:
module rxbb_lp_wrapper


  (

  
    bbmux_lp_n_ai_amplitude ,
    bbmux_lp_n_ai_frequency ,
    bbmux_lp_n_ai_phase ,
    bbmux_lp_p_ai_amplitude ,
    bbmux_lp_p_ai_frequency ,
    bbmux_lp_p_ai_phase ,
    lp_n_ai_amplitude ,
    lp_n_ai_frequency ,
    lp_n_ai_phase ,
    lp_p_ai_amplitude ,
    lp_p_ai_frequency ,
    lp_p_ai_phase ,
    lp1_n_amux_ao,
    lp1_p_amux_ao,
    lp2_n_amux_ao,
    lp2_p_amux_ao,
    lp_n_ao,
    lp_p_ao
    );
	  
  input   bbmux_lp_n_ai_amplitude ;
  input   bbmux_lp_n_ai_frequency ;
  input   bbmux_lp_n_ai_phase ;
  input   bbmux_lp_p_ai_amplitude ;
  input   bbmux_lp_p_ai_frequency ;
  input   bbmux_lp_p_ai_phase ;
  input   lp_n_ai_amplitude ;
  input   lp_n_ai_frequency ;
  input   lp_n_ai_phase ;
  input   lp_p_ai_amplitude ;
  input   lp_p_ai_frequency ;
  input   lp_p_ai_phase ;

  output  lp1_n_amux_ao;
  output  lp1_p_amux_ao;
  output  lp2_n_amux_ao;
  output  lp2_p_amux_ao;
  output  lp_n_ao;
  output  lp_p_ao;
  

  wreal   bbmux_lp_n_ai_amplitude ;
  wreal   bbmux_lp_n_ai_frequency ;
  wreal   bbmux_lp_n_ai_phase ;
  wreal   bbmux_lp_p_ai_amplitude ;
  wreal   bbmux_lp_p_ai_frequency ;
  wreal   bbmux_lp_p_ai_phase ;
  wreal   lp_n_ai_amplitude ;
  wreal   lp_n_ai_frequency ;
  wreal   lp_n_ai_phase ;
  wreal   lp_p_ai_amplitude ;
  wreal   lp_p_ai_frequency ;
  wreal   lp_p_ai_phase ;
  
  electrical  lp1_n_amux_ao;
  electrical  lp1_p_amux_ao;
  electrical  lp2_n_amux_ao;
  electrical  lp2_p_amux_ao;
  electrical  lp_n_ao;
  electrical  lp_p_ao;
  
  electrical	bbmux_lp_n_ai;
  electrical	bbmux_lp_p_ai;
  electrical	lp_n_ai;
  electrical	lp_p_ai;
  

   parameter tt=1u from [0:inf);

    analog begin
    V(bbmux_lp_n_ai) <+ transition(bbmux_lp_n_ai_amplitude, 0, tt)*sin(transition(bbmux_lp_n_ai_frequency, 0, tt)*$abstime + transition(bbmux_lp_n_ai_phase, 0, tt)) + transition(0, 0, tt);
    $bound_step(10/bbmux_lp_n_ai_frequency);
    V(bbmux_lp_p_ai) <+ transition(bbmux_lp_p_ai_amplitude, 0, tt)*sin(transition(bbmux_lp_p_ai_frequency, 0, tt)*$abstime + transition(bbmux_lp_p_ai_phase, 0, tt)) + transition(0, 0, tt);
    $bound_step(10/bbmux_lp_p_ai_frequency);
    V(lp_n_ai) <+ transition(lp_n_ai_amplitude, 0, tt)*sin(transition(lp_n_ai_frequency, 0, tt)*$abstime + transition(lp_n_ai_phase, 0, tt)) + transition(0, 0, tt);
    $bound_step(10/lp_n_ai_frequency);
    V(lp_p_ai) <+ transition(lp_p_ai_amplitude, 0, tt)*sin(transition(lp_p_ai_frequency, 0, tt)*$abstime + transition(lp_p_ai_phase, 0, tt)) + transition(0, 0, tt);
    $bound_step(10/lp_p_ai_frequency);
    end
    
  
    // Instantiate the analog netlist
  rxbb_lp rxbb_lp_inst(
    .bbmux_lp_n_ai(bbmux_lp_n_ai) ,
    .bbmux_lp_p_ai(bbmux_lp_p_ai) ,
    .lp_n_ai(lp_n_ai) ,

    .lp_p_ai(lp_p_ai) ,
    .lp1_n_amux_ao(lp1_n_amux_ao) ,
    .lp1_p_amux_ao(lp1_p_amux_ao) ,
    .lp2_n_amux_ao(lp2_n_amux_ao) ,
    .lp2_p_amux_ao(lp2_p_amux_ao) ,
    .lp_n_ao(lp_n_ao) ,
    .lp_p_ao(lp_p_ao)
  );
  

endmodule 



I have declared the inputs of the wrapper as wreal and my intermediate inputs as electrical and my final outputs as electrical.
When I execute this model, which is actually being instantiated in a bigger model;
I come across this error:
xmelab: *E,CUVNCM (../rxbb_lp_wrapper_13_puducodenarp/vams/testfixture_reference_rxbb_lp_model_wra
pper.vams,190|39): No connection module found:Need an input port of continuous discipline electrical, and a wreal output port of discrete discipline logic, at instance tb_rxbb_lp_model_wrapper.converter_shell_reference_rxbb_lp_model_wrapper_inst.te
stfixture_reference_rxbb_lp_model_wrapper_inst.reference_rxbb_lp_wrapper_inst, between actual port lp_p_ai_frequency and formal port lp_p_ai_frequency.
   .lp_p_ai_phase(lp_p_ai_phase) ,
For all the 12 input parameters I have used:
should be defined as wreal or can I change it to a suitabe option ?
The module that instantiates this module has defined it as
electrical  bbmux_lp_p_ai_phase.

8  Design / Mixed-Signal Design / Re: Verilog AMS sine generator
 on: Jan 14th, 2022, 1:09pm 
Started by Praseetha Pn | Post by Ken Kundert
Oh, one last thing.  The argument to a sine function is phase, and phase is the integral  of frequency.  You can only use sin(ωt) if ω is a constant.  If you are only interested in the output of the generator when ω is constant and you are okay with either very high or very low frequencies during changes, then you can continue to use sin(ωt).  This is generally preferred when creating testbench components.  Otherwise you should compute the phase using the idtmod operator.  You would need to do this when modeling a VCO.

9  Design / Mixed-Signal Design / Re: Verilog AMS sine generator
 on: Jan 14th, 2022, 1:01pm 
Started by Praseetha Pn | Post by Ken Kundert
Let me focus on a simplified example.

First consider the sine generator as a simple component with no hierarchy.  Conceptually it is as simple as this:
Code:
    module sinegen(out, freq, ampl, phase, offset);
    output electrical out;
    input wreal freq, ampl, phase, offset;

    analog V(out) <+ ampl*sin(freq*$abstime + phase) + offset;
    endmodule
 



I'm don't really understand why you want to instantiate the filter in the generator, but conceptually here is how you would do it:
Code:
    module sinegen(out, freq, ampl, phase, offset);
    output electrical out;
    input wreal freq, ampl, phase, offset;
    electrical in;

    lpf(.o(out), .i(.in));

    analog V(in) <+ ampl*sin(freq*$abstime + phase) + offset;
    endmodule
 



Having said that, this generator has a number of issues.  First, it is filled with discontinuities.  They should be eliminated with transition functions.
Code:
    module sinegen(out, freq, ampl, phase, offset);
    output electrical out;
    input wreal freq, ampl, phase, offset;
    parameter tt=1u from [0:inf);

    analog V(out) <+ transition(ampl, 0, tt)*sin(transition(freq, 0, tt)*$abstime + transition(phase, 0, tt)) + transition(offset, 0, tt);
    endmodule
 



For efficiency sake you want to make the transition time tt as long as possible.

Second, when you are generating a high frequency output when there is no corresponding high frequency input, you need to inform the simulator so you don't get aliasing.  You do that by adding a bound on the time step.
Code:
    module sinegen(out, freq, ampl, phase, offset);
    output electrical out;
    input wreal freq, ampl, phase, offset;
    parameter tt=1u from [0:inf);

    analog begin
	  V(out) <+ transition(ampl, 0, tt)*sin(transition(freq, 0, tt)*$abstime + transition(phase, 0, tt)) + transition(offset, 0, tt);
	  $bound_step(10/freq);
    endmodule
 



I use ten points per period.  You probably need at least 4, but realize that the larger you make this number the slower you simulation will be.

Finally, you need to synchronize your kernels, meaning that you need to force the analog simulator to place time points at the events in the digital inputs.  Conceptually you can do that with:
Code:
    module sinegen(out, freq, ampl, phase, offset);
    output electrical out;
    input wreal freq, ampl, phase, offset;
    parameter tt=1u from [0:inf);

    analog begin
	  @(freq or ampl or phase or offset)
		;
	  V(out) <+ transition(ampl, 0, tt)*sin(transition(freq, 0, tt)*$abstime + transition(phase, 0, tt)) + transition(offset, 0, tt);
	  $bound_step(10/freq);
    endmodule
 



I say conceptually because even though that is legal Verilog-AMS code, Cadence has never supported arbitrary events in the analog block, so it must be rewritten as:
Code:
    module sinegen(out, freq, ampl, phase, offset);
    output electrical out;
    input wreal freq, ampl, phase, offset;
    parameter tt=1u from [0:inf);
    reg break = 0;

    always @(freq or ampl or phase or offset) break <= !break;

    analog begin
	  @(posedge break or negedge break)
		;
	  V(out) <+ transition(ampl, 0, tt)*sin(transition(freq, 0, tt)*$abstime + transition(phase, 0, tt)) + transition(offset, 0, tt);
	  $bound_step(10/freq);
    endmodule
 



I just typed this code in from memory, so it might not work as given. But hopefully you find it useful.


10  Design / Mixed-Signal Design / Re: Verilog AMS sine generator
 on: Jan 14th, 2022, 12:20pm 
Started by Praseetha Pn | Post by Praseetha Pn
Hi,
Yes as of now I do not see an issue with that.
1. The input to my wrapper is amplitude, frequency and phase
2. But my DUT is an Low pass filter  and I want to drive a signal as input (sine signal).
I want to know how to generate this sine wave in my wrapper ?
what should be the type of this variable be, as it is not an input/output to my wrapper, but only an input to my DUT.

I have tried to create it in my previous code snip but does not work.

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