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Mar 19th, 2025, 7:35pm
1  Design / Mixed-Signal Design / System verilog modeling and simulation in cadence
 on: Feb 6th, 2025, 3:32pm 
Started by Yashas | Post by Yashas
Hi everyone,
I am new to system verilog modeling and my task is to model the 741 opamp using system verilog in as much detail as possible.

I was able to create a simple verilog description code, but the ADE simulator does not support simulating system verilog, a "corrupt netlist" notification pops up and after going through a couple of online material apparently spectre does not simulate system verilog.

Could some one recommend the appropriate steps to simulate the same on ADE or if there is an alternate tool that can be used?

FYI. I am limited to the DFII framework on cadence through the license my university uses. Other AMS tools are unavailable to me.

Thank You.

2  Design / Mixed-Signal Design / Re: Verilog AMS sine generator
 on: Jan 8th, 2025, 3:46pm 
Started by Praseetha Pn | Post by zhl101
Hello!

I'm working on a very similar module, modeling a commercialized oscillator as a CW sine wave source. I'm seeing a problem on discontinuity and aliasing, although I have set Cadence's min. time step to only 1ps. Since I'm modeling a 5GHz CW source, how should I define the tt here accordingly? Should tt be way smaller than the period of such sine wave? Thank you!

As a reference, here's the code:

Code:
`include "disciplines.vams"
`include "constants.vams"

module CW_source(out);
	voltage out;
	output out;
    // Parameters for configuration
    parameter real freq_center = 5e9; // Center frequency in Hz
    parameter real amplitude = 0.4; //sine amplitude
	parameter real offset = 0.4; //offset voltage

    // Phase noise profile
    parameter real phase_noise_offsets[5:0] = {10, 100, 1e3, 1e4, 1e5, 1e6}; // Offsets in Hz
    parameter real phase_noise_dBc[5:0] = {-63, -93, -118, -135, -136, -136}; // dBc/Hz

    // Harmonics and sub-harmonics
    parameter real harmonic_amplitudes_dBc = -25; // Harmonics < -25 dBc
    parameter real subharmonic_amplitude_dBc = -60; // Sub-harmonics < -60 dBc

    // PLL and spurious tones
    parameter real pll_amplitude_dBc = -60; // PLL & divider products < -60 dBc
    parameter real spur_amplitude_dBc = -80; // Spurious tones < -80 dBc

    // Internal signals
    real phase = 0.0;
    real phase_noise;
    real noise_contrib;
    real harmonic_amplitude, subharmonic_amplitude, pll_amplitude, spur_amplitude;
    genvar i, h;

    analog begin
	  // Time-step calculation
	  // Base phase update for center frequency
	  phase = phase + 2.0 * `M_PI * freq_center * $abstime;

	  // Add phase noise contributions
	  phase_noise = 0.0;

		for (i=0; i<6; i=i+1)
		begin
			noise_contrib = $rdist_normal(23, 0, 10**(phase_noise_dBc[i] / 20));
			phase_noise = phase_noise + noise_contrib * sin(2.0 * `M_PI * phase_noise_offsets[i] * $abstime);
		end
		phase = phase + phase_noise;

	  // Initialize output signal

	  // Add harmonics
		harmonic_amplitude = amplitude* (10**(harmonic_amplitudes_dBc / 20)); // Convert dBc to linear
	  for (h=2; h<=5; h=h+1)
		V(out) <+ harmonic_amplitude * sin(h * phase);

	  // Add sub-harmonics
	  subharmonic_amplitude = amplitude* (10**(subharmonic_amplitude_dBc / 20)); // Convert dBc to linear
	  V(out) <+ subharmonic_amplitude * sin(0.5 * phase); // Half-frequency sub-harmonic
	    V(out) <+ subharmonic_amplitude * sin(0.25 * phase); // Quarter-frequency sub-harmonic

	  // Add PLL & divider products
	  //pll_amplitude = amplitude * (10**(pll_amplitude_dBc / 20)); // Convert dBc to linear
	  //V(out) <+ pll_amplitude * sin(2.0 * `M_PI * (freq_center / 4) * $abstime); // Example product

	  // Add spurious tones
	  spur_amplitude = amplitude * (10**(spur_amplitude_dBc / 20)); // Convert dBc to linear
	  V(out) <+ spur_amplitude * sin(2.0 * `M_PI * (freq_center - 1e9) * $abstime); // Example spur
    end
endmodule

 


3  Design / Analog Design / Re: A question on STB analysis of OSC
 on: Dec 2nd, 2024, 5:35pm 
Started by chang830 | Post by chang830
Dear Sheldon,  I use stability analysis. I think in the beginning of the buildup, it is linear.

4  Design / Analog Design / Re: A question on STB analysis of OSC
 on: Dec 2nd, 2024, 10:39am 
Started by chang830 | Post by sheldon
Chang,

  Are you using stability analysis or periodic stability analysis?

                                                                        Sheldon

5  Design / Analog Design / A question on STB analysis of OSC
 on: Dec 2nd, 2024, 5:07am 
Started by chang830 | Post by chang830
Hi , I have  a problem on simulation of xtal oscillator. When I simulatie a Santos xtal OSC, I use STB to get its gainmargin which I found it is -1.5dB.So it should not to oscillate, but I found it can oscillate corectly when I use transisent analysis.  Can anyone explain this descranpcy?

Thanks a lot!

6  Simulators / Circuit Simulators / How to integrate Calibre with Cadence Virtuoso?
 on: Nov 12th, 2024, 11:33pm 
Started by Yameng | Post by Yameng
Hi all,

I'm currently using a separate Calibre gui from Cadence, and learned from this vid(https://www.youtube.com/watch?v=oMZZ9q3f10A&list=PLP4ZmM6GPuePeV6zkmb0wVBm11xplE...) , that there's a way to merge those tools together.

An edaboard post( https://www.edaboard.com/threads/how-to-add-calibre-into-virtuoso.23011/) mentioned I need first to create a .cdsinit file.

But I'm unsure where I should create the file.

Anyways, does anyone know where I can find more information abt it?

Thanks a lot:)

7  Design / RF Design / Re: Dead Zone problem in PLL
 on: Nov 3rd, 2024, 10:47pm 
Started by rajasekhar | Post by baohulu
smlogan wrote on Jun 8th, 2023, 5:31pm:
Dear Raj,

as you said below

" Intuitively, the presence of the dead-zone means that for phase differences between the reference clock and feedback clock that are within the dead-zone, the VCO will be running open loop and hence the low frequency phase noise will mimic the open loop VCO phase noise."




I want to know in the above case, how "low frequency" will the vco PN contribute to the pll PN. if the pfd dead zone time window is 100ps, and in your case, fref=10M, divider ratio=10, fvco=100MHz, then, what is the frequency range of the vco phase noise will be the pll phase noise?

thanks

8  Design / RF Design / How to generate j*cos(wt) in a single physical wire?
 on: Oct 21st, 2024, 10:48am 
Started by vlsi_design | Post by vlsi_design

Hi, How can one generate j*coswt in the lab from coswt available in single physical wire? Please note that intention is to multiply both positive and negative frequency content with +j. I am not asking about hilbert transform which is -90 degree phase shift and rotates positive frequency content with -j and negative content with +j. Also, I am not asking about a anticlockwise phasor rotation of 90 degree or phasor multiplication by +j because phasor is e^jwt and not coswt. Is it necessary to have 2 physical wires and force orthogonality?


9  Design / Analog Design / how to set abstol(U) in pss/tstab of virtuoso?
 on: Aug 28th, 2024, 8:38pm 
Started by argention | Post by argention
When I run the DC-DC BUCK pss simulation in virtuoso, the pss does not converge, and the error is max dU exceeded. just like this:
Conv norm = 2.57e+03, max dU(NPORT32:s7) = 3.7374 , took 5.45 s
Conv norm = 1.77e+03, max dU(NPORT32:s7) = -2.55048 , took 5.13 s

I found in spectre.out that the default setting for abstol (U) is 1 u. just like this:
Important parameter values in tstab integration:
start = 0 s
......
abstol(V) = 3 mV
abstol(I) = 1 A
abstol(U) = 1 u
.......
I want to change abstol(U) to a larger value, but I don't know where to set it. Can anyone help me? Thanks a lot!

10  Simulators / RF Simulators / Re: How to extract s2p files for sp probe in ADS?
 on: Jul 5th, 2024, 10:48am 
Started by Yashas | Post by Ken Kundert
Can you be more specific as to what you want? Extract from what?

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