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Jun 24th, 2019, 7:16pm
1  Design Languages / Verilog-AMS / Re: transition filter rise and fall time delay not working as expected
 on: Today at 5:42am 
Started by sanforyou | Post by sanforyou
One more quick question, If I don't use transition filter at all on LSG_switch (as shown in below code) then I still see fall time delay of about 10ps on the PH node high to low transition as shown in the attached waveform. What controls this fall time? Can I change it to a different value?

 analog begin
     //@(posedge LSG_sns)
     //;

Code:
    I(PVIN,PH) <+ 100.0p*ddt(V(PVIN,PH));
    I(PH,PVIN) <+ is*(limexp(V(PH,PVIN)/(N*$vt))-1.0) + V(PH,PVIN)*1p;

    I(PH,PGND) <+ 100.0p*ddt(V(PH,PGND));
    I(PGND,PH) <+ is*(limexp(V(PGND,PH)/(N*$vt))-1.0) + V(PGND,PH)*1p;

    //ss_test=transition(LSG_switch,0,500.0p,500.0p);
    I(PVIN,PH) <+ V(PVIN,PH)/transition(HSG_switch,0,500.0p,500.0p);
    I(PH,PGND) <+ V(PH,PGND)/LSG_switch;
    V(PH_SNS,PGND) <+ V(PH,PGND);
    V(PGND_SNS) <+ V(PGND);
  end 


2  Design Languages / Verilog-AMS / Re: transition filter rise and fall time delay not working as expected
 on: Today at 4:52am 
Started by sanforyou | Post by sanforyou
That's good to know. After your comment I checked decrease in magnitude of transition filter output("ss_test") after LSG_switch goes high to low and I noticed that decrease in magnitude is very small at first few analog time points. It decreases like this: 1e(+09)->8.37e(+08)->5.1e(+08) and so on. That means its still pretty high to make any change to PH node noticeable. However "ss_test" decreases rapidly at the end of 500ps when you actually see the fall time transition on PH node.

All I'm trying to do is to switch PH node similar to "ss_test" because that's how actual transistor schematic behaves. That means I need 'ss_test' to decrease rapidly at the beginning to make PH node transition similar to "ss_test".  Is there a way to achieve this?

3  Design Languages / Verilog-AMS / Re: transition filter rise and fall time delay not working as expected
 on: Yesterday at 9:04pm 
Started by sanforyou | Post by Ken Kundert
Good there is an analog time point at the time when LSG_switch changes.  So I think the transition function is working properly.

I believe the behavior you are seeing is the actual behavior of the circuit. With ideal switches where the switch resistance sweeps over a very large range that the circuit reacts most strongly at the very end of the range.

-Ken

4  Design / Mixed-Signal Design / Re: TSMC 65nm Calibre dummy insertion tool
 on: Yesterday at 7:17pm 
Started by allendmh | Post by satyamishra
Hi MD,

It's hard to tell from your description. Couple of things jump out:
1. Are you sure you are using GDSII, as your Layout System command indicates, and not using OpenAccess directly?
2. Have you set the DRC rule switches correctly for you process?

Regards,
Satya

PS, this is probably not the right forum for this question

5  Design Languages / Verilog-AMS / Re: transition filter rise and fall time delay not working as expected
 on: Yesterday at 1:41pm 
Started by sanforyou | Post by sanforyou
Here is how it looks after enabling Format->Symbol->points and lines

6  Design Languages / Verilog-AMS / Re: transition filter rise and fall time delay not working as expected
 on: Yesterday at 10:01am 
Started by sanforyou | Post by Ken Kundert
Sorry, I meant Format->Symbol->Points and Lines.

7  Design Languages / Verilog-AMS / Re: transition filter rise and fall time delay not working as expected
 on: Yesterday at 7:49am 
Started by sanforyou | Post by sanforyou
Part 3 of the code

8  Design Languages / Verilog-AMS / Re: transition filter rise and fall time delay not working as expected
 on: Yesterday at 7:48am 
Started by sanforyou | Post by sanforyou
Part 2 of the code

9  Design Languages / Verilog-AMS / Re: transition filter rise and fall time delay not working as expected
 on: Yesterday at 7:47am 
Started by sanforyou | Post by sanforyou
Part one of the code

10  Design Languages / Verilog-AMS / Re: transition filter rise and fall time delay not working as expected
 on: Yesterday at 7:44am 
Started by sanforyou | Post by sanforyou
Hi Ken,
I added code you suggested to synchronize the time step when LSG_switch changes but it doesn't seem to make any difference to PH node output.

I have attached waveform showing analog time points to show delay between LSG_switch transition and transition filter output.  I have also attached complete code in case it helps you to find out what might be the issue in the code causing PH node not to transition as expected?

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