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Jul 11th, 2020, 11:56pm
1  Modeling / Behavioral Models / Re: VCO Phase Noise 40dB/dec instead of 20dB/dec in PNoise
 on: Jul 9th, 2020, 12:43pm 
Started by Hudson | Post by Hudson
Hi Ken,

Thanks for your reply.

Yes, the contribution from the wpn_osc is 100% at 1MHz and 10MHz offset. I also checked the vn spectrum to be white.

2  Design / RF Design / Varactor equivalent capacitance
 on: Jul 9th, 2020, 1:37am 
Started by Marios | Post by Marios
Dear all,

I have a question with regards to varactors:

  Assume we have an ideal varactor whose C-V relationship is a straight line, for example C = a*v(t). Now assume that our varactor is driven by a pure sinusoid such that v(t) = cos(ω*t).
  If I wanted to replace my varactor by a constant capacitor that would produce the same effect what would the constant capacitor’s equivalent value have to be?

(a)      The varactor’s average capacitance value over a period
(b)      The varactor’s RMS capacitance value
(c)      It depends; If we are after equivalent capacitor that would require the same reactive power we use the RMS value but if we are after an equivalent capacitance for tuning (using an inductor lets say) we use the average value

There are two papers that analyse this but each one of them takes its own approach; one of them takes the rms value while the other assumes that the varactor's capacitance can be approximated by a Fourier series. To this end I would assume that the equivalent value would be the 1st Fourier term, ie the average value of the varactor. This issue stems in LC-VCOs where the signal swing is large enough as to cause the varactor's value to depart significantly. The two papers are:

https://ieeexplore.ieee.org/document/1202006
https://ieeexplore.ieee.org/document/1214725

Any answer is appreciated.

Regards
Marios


3  Modeling / Behavioral Models / Re: VCO Phase Noise 40dB/dec instead of 20dB/dec in PNoise
 on: Jul 8th, 2020, 4:18pm 
Started by Hudson | Post by Ken Kundert
I don't see an obvious cause for your symptoms in the model you gave.  The next step would be to plot the contributors to the VCO output noise to see if it can be attributed to wpn_osc.

-Ken

4  Modeling / Behavioral Models / VCO Phase Noise 40dB/dec instead of 20dB/dec in PNoise
 on: Jul 8th, 2020, 12:04pm 
Started by Hudson | Post by Hudson
Hi all,

I am using verilog to model VCO with phase noise.

The VCO frequency is the summation of f0 + Kvco*Vcont + white_noise and I calculate the phase with the idtmod function.

"
wn1 = 2*pow(Fos,2)*pow(10,(phasenoise/10));
     V(vn)<+white_noise(wn1, "wpn_osc");
   freq = (V(in) - vmin)*(fmax - fmin) / (vmax - vmin) + fmin + V(vn);
   phase = 2*`M_PI*idtmod(freq, 0.0, 1.0, -0.5);

   V(out) <+ va*sin(phase);
"
However, the phase noise has 40dB/dec roll-off in Pnoise simulation, which supposedly should be 20dB/dec. I also check that vn is white indeed. Then I did an experiment to directly add white noise to the phase, the output phase noise turns out to be 20dB/dec roll-off now. I do not know where the problem could be.



The full code is attached below

module vco0 (out, in , vn);

input in; voltage in;                           // input terminal
output out; voltage out;                        // output terminal
output vn; voltage vn;
parameter real vmin=0;                          // input voltage that corresponds to minimum output frequency
parameter real vmax=vmin+1 from (vmin:inf);     // input voltage that corresponds to maximum output frequency
parameter real fmin=1 from (0:inf);             // minimum output frequency
parameter real fmax=2*fmin from (fmin:inf);     // maximum output frequency
parameter real va=1;                            // amplitude

parameter real Fos = 1M;// from (0:inf);  // offset frequency at which phase noise is given
parameter real phasenoise = -120 from [-400:inf); // phase noise level

real wn1; // noise sources
real freq, phase;
integer n;

//voltage vn;

analog begin
   // compute the freq from the input voltage
     wn1 = 2*pow(Fos,2)*pow(10,(phasenoise/10));
     V(vn)<+white_noise(wn1, "wpn_osc");
   freq = (V(in) - vmin)*(fmax - fmin) / (vmax - vmin) + fmin + V(vn);
     

   // bound the frequency (this is optional)
  // if (freq > fmax) freq = fmax;
  // if (freq < fmin) freq = fmin;

   // bound the time step to assure no cycles are skipped
   $bound_step(0.1/freq);

   // phase is the integral of the freq modulo 2 pi
   phase = 2*`M_PI*idtmod(freq, 0.0, 1.0, -0.5);

   V(out) <+ va*sin(phase);
end
endmodule


5  Design / Analog Design / Re: Amplifier 2nd second stage topology clarification
 on: Jul 7th, 2020, 4:33am 
Started by Chetan Kulkarni | Post by Chetan Kulkarni
I wanted to decide on the second stage of 1st amplifier ...(meaning Class AB output stage or Class A stage)

6  Design / Analog Design / Re: Full scale voltage of a delta sigma modulator
 on: Jul 3rd, 2020, 7:56am 
Started by saralandry | Post by saralandry
Thanks Tako.

So, if I'v understood correctly,

1- for a single-ended delta sigma, if we want to have an input full scale of e.g. VFS we need to set the reference voltage of the feedback DAC to two times of the VFS (i.e. Vrefn=0 and Vrefp= 2*VFS)

For a fully differential delta sigma, if want to have an input full scale of VFS, we need to set the reference voltage of the DAC to VFS (i.e. Vrefn=0 and Vrefp=VFS).

Am I right?

7  Design / Analog Design / Re: Trade-off between LDO max Iout AND PSRR
 on: Jul 2nd, 2020, 5:17am 
Started by blue111 | Post by blue111
I am asking about "changing m of both M12 and M16 to m=8"

8  Design / Analog Design / Re: Trade-off between LDO max Iout AND PSRR
 on: Jul 2nd, 2020, 4:51am 
Started by blue111 | Post by Tako
blue111 wrote on Jul 2nd, 2020, 4:28am:
WHY if I remove Cout and change values of m of both M12 and M16 to m=8 , then it gives good phase margin (phase plot starts at 180 degree (negative feedback) and decreases monotonously. When it crosses the 0 degree with magnitude >= 0 dB, the feedback circuit is unstable according to Bode stability criterion.) ?

Because Cout should be rather expected to be one of the main poles.



blue111 wrote on Jul 2nd, 2020, 4:28am:
WHY doing so will result in a trade-off of a much larger load regulation spike (800mV) in Vout ?

Because, now there is no big capacitance at the output, so the output voltage may rise faster and hence the spikes.

9  Other CAD Tools / Entry Tools / Re: FreePDK45 usage in Virtuoso
 on: Jul 2nd, 2020, 4:44am 
Started by blue111 | Post by Tako
Great. Thank you for the feedback. This one was one of the expected problems.

10  Design / Analog Design / Re: Amplifier 2nd second stage topology clarification
 on: Jul 2nd, 2020, 4:38am 
Started by Chetan Kulkarni | Post by Tako
Hi,

Where exactly you would like to put another opamp?

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