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Apr 3rd, 2020, 4:23am
1  Design / Analog Design / 100 MHz oscillator on ~0.18um CMOS
 on: Apr 1st, 2020, 9:57pm 
Started by AnalogDE | Post by AnalogDE
Can someone suggest a good architecture for a ~100MHz oscillator?
I need good PVT performance (~ +/- 10% period variation)


2  Simulators / RF Simulators / Re: PAC and PSTB for switched capacitor integrator
 on: Mar 29th, 2020, 12:42pm 
Started by iVenky | Post by Ken Kundert
It is strange that your circuit is running in its normal operating region. Just applying a square wave input with 0 DC level should not work unless your integrator has low gain. Even with an input with 0 DC level, any offsets or leakages in the circuit should cause the output of the integrator to saturate.

I suspect that whatever is keeping your circuit in its normal operating mode is also responsible for dropping your gain at low frequencies.

-Ken

3  Simulators / Circuit Simulators / Re:  Sampling Bandwidth vs. Bandwidth in Tracking Mode of a Sample/Track and Hold
 on: Mar 29th, 2020, 12:36pm 
Started by repah | Post by Ken Kundert
To measure the sample bandwidth, use a PXF analysis where you sweep the output frequency from 0 to fs/2. Set max sidebands to something large, say 20-100. Run the analysis and plot the results including all sidebands by using the spectrum mode in direct plot. You can measure the sample bandwidth from the envelope of all the transfer functions.

To measure the bandwidth in track mode, simply turn off the clock and run an AC analysis.

-Ken

4  Simulators / Circuit Simulators / Re: IP3 Simulation of a Sample and Hold Circuit in Spectre
 on: Mar 29th, 2020, 12:30pm 
Started by repah | Post by Ken Kundert
There is no need for the clock/LO to be a sinusoid. The only restriction is that the signal be periodic.

Why is f1 2GHz? Why is f1 a multiple of the clock?

A sample and hold is broad band, so why not simply use harmonic distortion rather that intermodulation distortion?

-Ken

5  Simulators / Circuit Simulators / Re: IP3 Simulation of a Sample and Hold Circuit in Spectre
 on: Mar 29th, 2020, 1:34am 
Started by repah | Post by repah
Thank you Mr. Kundert.

But this system is clocked, do I use a SINE for my LO (clock port in sampling application) versus a PULSE.

I notice when simulating mixers - the LO is defined as a SINE even though it is a pulse.

Why is this ?

Also following the example in your application note:

My LO is the clocking frequency of the sample and hold, say 50MHz.

My f1 is the input frequency of the sample and hold, say 2GHz.

I use 51MHz as an f2.

In QPSS, I set LO to be large signal and f1 to be moderate.

Then in QPAC I set my f2 to be 51MHz.

I do this, and I don't get a reasonable response, but I used PULSE on my ports for clock/lo and not SINE.

What am I doing wrong ?

6  Simulators / Circuit Simulators / Sampling Bandwidth vs. Bandwidth in Tracking Mode of a Sample/Track and Hold
 on: Mar 28th, 2020, 5:05pm 
Started by repah | Post by repah
What is the difference between the Sampling Bandwidth vs. Bandwidth in Tracking Mode of a Sample/Track and Hold Amplifier ?

Is Bandwidth in tracking mode different then the sampling bandwidth ?

How would I find these using Cadence Spectre simulation ?

7  Simulators / RF Simulators / Re: PAC and PSTB for switched capacitor integrator
 on: Mar 27th, 2020, 11:28am 
Started by iVenky | Post by iVenky
Hi Ken,

Thanks for the reply. I have verified the output of op-amp is in nominal operation range. In fact, what I am doing here is emulating the condition when the integrator is used inside an sdm with vin=0, which results in 10101010 limit cycle output. The way I do this is by switching V+ and V- back and forth by modulating the corresponding switches so that there is equal charge and discharge forcing the op-amp into this periodic state.  

I have a question about stability. I see the PSTB output is shaped by the integrator transfer function (shows something like the one I have attached (blue curve is what i see for pstb loop gain)). Is this expected when run pstb for an integrator, as it's integrating. I don't see this on the other hand if I, say, reset the capacitor C2 each cycle, thereby making it work like a switched capacitor amplifier & the effective transfer function looks like op-amp transfer function.

As far as pnoise is concerned, I am now trying to replicate what you mentioned in your document (using track and hold feedback) and see if I can measure it closed loop.

https://designers-guide.org/analysis/delta-sigma.pdf

UPDATE: the pnoise method using track & hold feedback does seem to work and match with tran noise simulation if I integrate till fclk/2. Why does sampled pnoise show values beyond fclk/2. It doesn't make sense. Also, this method is valid only upto frequencies until which PAC gain >1, right? Beyond that it may be over-estimating the noise

Also, why does the closed loop gain in Fig 15 of this reference (https://designers-guide.org/analysis/delta-sigma.pdf) show a value > 1? Since it's in unity gain feedback, I expect that number to be equal to 1.

8  Simulators / RF Simulators / Re: PAC and PSTB for switched capacitor integrator
 on: Mar 27th, 2020, 10:48am 
Started by iVenky | Post by Ken Kundert
One thing that might explain your results is if your amplifier was in clipping. Did you check the time-domain waveforms to confirm that the amplifier is always in its normal operating range.

The challenge with this circuit is to get the circuit settle to a periodic operating point that is inside the normal operating range of the amplifier. I think if you can do that the normal approaches to computing noise and stability would work. But without some kind of feedback I cannot see how that will happen.

Normally I council against using a very low pass filter to provide feedback at DC, but that is what you might have to do here.

-Ken

9  Simulators / Circuit Simulators / Re: IP3 Simulation of a Sample and Hold Circuit in Spectre
 on: Mar 27th, 2020, 10:31am 
Started by repah | Post by Ken Kundert
From a simulators perspective, a clocked sample and hold is no different from a mixer where the clock plays the role of the LO.

I recommend you following the instructions in Accurate and Rapid Measurement of IP2 and IP3. See section 7.

-Ken

10  Simulators / Circuit Simulators / IP3 Simulation of a Sample and Hold Circuit in Spectre
 on: Mar 26th, 2020, 10:32pm 
Started by repah | Post by repah

I want to measure the IP3 of a Sample and Hold (clocked) using Cadence Spectre.

What is the best procedure for this ? QPSS or PSS ?

I want to sweep over input voltage.

The circuit diagram is attached.  Just a simple tgate switch with a hold cap clocked at 2GHz, followed by a buffer then another tgate switch and a hold cap.

Input is a 50Mhz sine wave at 5mV.

Do I follow advice in application note - simulating switched capacitor filters on this forum - ie. do QPSS ?  How is this setup for a clock and an rf input, if using QPSS ?

Thank you.

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