Designer’s Guide Community

Pages: 1 2 3 ... 47

Subject	Started by	Replies	Views	Last post
Delay Line	Cascody	0	103	Feb 4^th, 2021, 10:46pm By: Cascody
How to compare Matlab/Theory <=> Cadence: Switched-cap. integrator: Mag	bernd2700	10	295	Jan 22^nd, 2021, 4:12am By: bernd2700
sigma delta adc concept	saralandry	1	192	Jan 15^th, 2021, 3:01am By: bernd2700
open loop VCO-Based ADC	zahramoh	11	610	Dec 17^th, 2020, 2:50am By: zahramoh
Unusal FFT of the ADC Output	niloun	5	327	Nov 2^nd, 2020, 2:26pm By: polyam
How do you simulate or define DNL/INL for a 1-bit Delta Sigma ADC for a dc input	iVenky	2	307	Oct 12^th, 2020, 3:50pm By: iVenky
Self-calibrating Comparator in SAR ADC	vm511	0	222	Aug 25^th, 2020, 4:10pm By: vm511
Integration Limits in Papers	subtr	1	411	Jun 10^th, 2020, 4:10pm By: dnw
Charge Redistribution DAC caliberation	Cascody	0	184	May 31^st, 2020, 6:04am By: Cascody
Moved: Time Interleaved ADC - Started by: repah This Topic has been moved to Behavioral Models by Ken Kundert
Moved: MUX Element in AnalogLib or ahdlLib in Cadence for Time Interleaved ADC - Started by: repah This Topic has been moved to Behavioral Models by Ken Kundert
Conversion Rate and Data Converters	repah	0	156	Apr 25^th, 2020, 3:13pm By: repah
ENOB - from SDR, SNDR, SFDR, ?	repah	1	253	Apr 21^st, 2020, 1:33pm By: DanielLam
clocking of a decimation filter and reading the output of a decimation filter	polyam	0	259	Jan 23^rd, 2020, 5:24pm By: polyam
Offset cancellation in switched capacitor circuit	vm511	2	559	Dec 13^th, 2019, 6:44am By: vm511
Stability analysis of a Bang-Bang CDR loop	Sumilak1994	1	640	Dec 13^th, 2019, 6:41am By: subtr
LDO Simulation Output Results	repah	1	360	Aug 30^th, 2019, 6:49am By: Horror Vacui
How to store the difference of 2 voltages on capacitor	josvlsi	1	1044	Aug 13^th, 2019, 12:07pm By: subtr
LDO Simulation - Cadence - ILoad vs. Vout - Line Regulation	repah	1	422	Aug 13^th, 2019, 11:53am By: subtr
Capacitor Selection in Sigma Delta Modulators	repah	0	302	Aug 13^th, 2019, 10:24am By: repah

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