Designer’s Guide Community

Pages: 1 2 3 ... 47

Subject	Started by	Replies	Views	Last post
Loop filter For PLL	Vikrant	0	70	Sep 22^nd, 2021, 7:34am By: Vikrant
Delay Line	Cascody	1	307	Jun 28^th, 2021, 1:13am By: Horror Vacui
How to simulate the "unlatched gain" of a dynamic comparator	wax and wane	1	194	Jun 28^th, 2021, 1:09am By: Horror Vacui
How to compare Matlab/Theory <=> Cadence: Switched-cap. integrator: Mag	bernd2700	10	616	Jan 22^nd, 2021, 4:12am By: bernd2700
sigma delta adc concept	saralandry	1	344	Jan 15^th, 2021, 3:01am By: bernd2700
open loop VCO-Based ADC	zahramoh	11	967	Dec 17^th, 2020, 2:50am By: zahramoh
Unusal FFT of the ADC Output	niloun	5	520	Nov 2^nd, 2020, 2:26pm By: polyam
How do you simulate or define DNL/INL for a 1-bit Delta Sigma ADC for a dc input	iVenky	2	457	Oct 12^th, 2020, 3:50pm By: iVenky
Self-calibrating Comparator in SAR ADC	vm511	0	337	Aug 25^th, 2020, 4:10pm By: vm511
Integration Limits in Papers	subtr	1	531	Jun 10^th, 2020, 4:10pm By: dnw
Charge Redistribution DAC caliberation	Cascody	0	272	May 31^st, 2020, 6:04am By: Cascody
Moved: Time Interleaved ADC - Started by: repah This Topic has been moved to Behavioral Models by Ken Kundert
Moved: MUX Element in AnalogLib or ahdlLib in Cadence for Time Interleaved ADC - Started by: repah This Topic has been moved to Behavioral Models by Ken Kundert
Conversion Rate and Data Converters	repah	0	220	Apr 25^th, 2020, 3:13pm By: repah
ENOB - from SDR, SNDR, SFDR, ?	repah	1	361	Apr 21^st, 2020, 1:33pm By: DanielLam
clocking of a decimation filter and reading the output of a decimation filter	polyam	0	340	Jan 23^rd, 2020, 5:24pm By: polyam
Offset cancellation in switched capacitor circuit	vm511	2	692	Dec 13^th, 2019, 6:44am By: vm511
Stability analysis of a Bang-Bang CDR loop	Sumilak1994	1	770	Dec 13^th, 2019, 6:41am By: subtr
LDO Simulation Output Results	repah	1	482	Aug 30^th, 2019, 6:49am By: Horror Vacui
How to store the difference of 2 voltages on capacitor	josvlsi	1	1174	Aug 13^th, 2019, 12:07pm By: subtr

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