Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
What will happen for the histogram of the ADC if the last conversion is not done	Jacki_2016	0	81	Aug 2^nd, 2022, 6:12am By: Jacki_2016
How does the kickback noise really infect on the resolution in SARADC?	Jacki_2016	2	166	Aug 2^nd, 2022, 6:07am By: Jacki_2016
How to understand the binary-weighted SARADC	Jacki_2016	0	68	Jun 17^th, 2022, 12:16pm By: Jacki_2016
Performing Monte-Carlo simulation with AMS	sutapanaki	0	66	Jun 16^th, 2022, 9:50am By: sutapanaki
Element for producing half and one clock cycle delay in Cadence	D-Generation X	6	428	Mar 15^th, 2022, 5:53am By: D-Generation X
Verilog AMS sine generator	Praseetha Pn	11	744	Feb 1^st, 2022, 1:22pm By: Ken Kundert
Moved: how to set initial state of digital circuit in AMS simulation? - Started by: unaffected This Topic has been moved to AMS Simulators by Forum Administrator
How to compare Matlab/Theory <=> Cadence: Switched-cap. integrator: Mag	bernd2700	11	1236	Oct 26^th, 2021, 6:42am By: Juliaw ebbiavx
Loop filter For PLL	Vikrant	0	298	Sep 22^nd, 2021, 7:34am By: Vikrant
Delay Line	Cascody	1	515	Jun 28^th, 2021, 1:13am By: Horror Vacui
How to simulate the "unlatched gain" of a dynamic comparator	wax and wane	1	365	Jun 28^th, 2021, 1:09am By: Horror Vacui
sigma delta adc concept	saralandry	1	559	Jan 15^th, 2021, 3:01am By: bernd2700
open loop VCO-Based ADC	zahramoh	11	1445	Dec 17^th, 2020, 2:50am By: zahramoh
Unusal FFT of the ADC Output	niloun	5	803	Nov 2^nd, 2020, 2:26pm By: polyam
How do you simulate or define DNL/INL for a 1-bit Delta Sigma ADC for a dc input	iVenky	2	621	Oct 12^th, 2020, 3:50pm By: iVenky
Self-calibrating Comparator in SAR ADC	vm511	0	492	Aug 25^th, 2020, 4:10pm By: vm511
Integration Limits in Papers	subtr	1	671	Jun 10^th, 2020, 4:10pm By: dnw
Charge Redistribution DAC caliberation	Cascody	0	387	May 31^st, 2020, 6:04am By: Cascody
Moved: Time Interleaved ADC - Started by: repah This Topic has been moved to Behavioral Models by Ken Kundert
Moved: MUX Element in AnalogLib or ahdlLib in Cadence for Time Interleaved ADC - Started by: repah This Topic has been moved to Behavioral Models by Ken Kundert

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