Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
System verilog modeling and simulation in cadence	Yashas	0	5122	Feb 6^th, 2025, 3:32pm By: Yashas
Verilog AMS sine generator	Praseetha Pn	12	8540	Jan 8^th, 2025, 3:46pm By: zhl101
how to calculate DNL if there are missing codes	A Kumar R	0	1329	Sep 6^th, 2023, 6:55am By: A Kumar R
Folding Effect: Choosing ADC Input Frequency to Observe Unwanted Tones	niloun	1	2403	Jun 9^th, 2023, 4:15pm By: niloun
Intergtared PGA design problems for delta sigma modulator	designer_ring	0	2083	Jan 15^th, 2023, 7:21pm By: designer_ring
What will happen for the histogram of the ADC if the last conversion is not done	Jacki_2016	1	2530	Jan 15^th, 2023, 10:34am By: smlogan
How does the kickback noise really infect on the resolution in SARADC?	Jacki_2016	2	3050	Aug 2^nd, 2022, 5:07am By: Jacki_2016
How to understand the binary-weighted SARADC	Jacki_2016	0	2168	Jun 17^th, 2022, 11:16am By: Jacki_2016
Performing Monte-Carlo simulation with AMS	sutapanaki	0	2089	Jun 16^th, 2022, 8:50am By: sutapanaki
Element for producing half and one clock cycle delay in Cadence	D-Generation X	6	5321	Mar 15^th, 2022, 4:53am By: D-Generation X
Moved: how to set initial state of digital circuit in AMS simulation? - Started by: unaffected This Topic has been moved to AMS Simulators by Forum Administrator
How to compare Matlab/Theory <=> Cadence: Switched-cap. integrator: Mag	bernd2700	11	7958	Oct 26^th, 2021, 5:42am By: Juliaw ebbiavx
Loop filter For PLL	Vikrant	0	2468	Sep 22^nd, 2021, 6:34am By: Vikrant
Delay Line	Cascody	1	2987	Jun 28^th, 2021, 12:13am By: Horror Vacui
How to simulate the "unlatched gain" of a dynamic comparator	wax and wane	1	2707	Jun 28^th, 2021, 12:09am By: Horror Vacui
sigma delta adc concept	saralandry	1	2161	Jan 15^th, 2021, 3:01am By: bernd2700
open loop VCO-Based ADC	zahramoh	11	7749	Dec 17^th, 2020, 2:50am By: zahramoh
Unusal FFT of the ADC Output	niloun	5	4520	Nov 2^nd, 2020, 2:26pm By: polyam
How do you simulate or define DNL/INL for a 1-bit Delta Sigma ADC for a dc input	iVenky	2	3362	Oct 12^th, 2020, 2:50pm By: iVenky
Self-calibrating Comparator in SAR ADC	vm511	0	2548	Aug 25^th, 2020, 3:10pm By: vm511

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