Problem with Ideal current steering DAC in a CT DSM

design consideration for a low noise dynamic comparator with preamp.

Moved: Sigma Delta Modulator SNDR with Monte-Carlo Simulation in Cadence - Started by: MehdiOranji
This Topic has been moved to Circuit Simulators by Ken Kundert

SRAM design for external EEPROM

Waveforms through Class E amplifier

Moved: Port declaration in ADC model - Started by: samiran
This Topic has been moved to Verilog-AMS by Ken Kundert

Moved: Evaluating PSD of Opamp/Data Converter in MATLAB from Cadence Spectre - Started by: repah
This Topic has been moved to Circuit Simulators by Ken Kundert

Moved: calculating SNR from dft on Spectre - Started by: iris
This Topic has been moved to Circuit Simulators by Ken Kundert

Moved: Fully Differential Opamp MacroModel in Cadence - Started by: repah
This Topic has been moved to Behavioral Models by Ken Kundert

SAR ADC Power Consumption

Moved: Resources usage - Started by: Abdullah
This Topic has been moved to Verilog-AMS by Ken Kundert

Real word ADC

Moved: POLY1 must be covered by N+ or P+ implant layer @Umc40lp using Calibre - Started by: Ramakrishna RSSM
This Topic has been moved to Physical Verification, Extraction and Analysis by Ken Kundert

Moved: How to substitute some source files while running irun command line? - Started by: BackerShu
This Topic has been moved to AMS Simulators by Ken Kundert

Comparator Vtrip in integrating ADC ?

A simple question regarding some verilog code

1.5 bit DAC

Metastability error probability of a cascade of latches

How to plot the sampling window of the Flipflop..?

variable frequency PWM modulators