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May 20th, 2019, 9:48am
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Why did the post-layout simulation result incorrectly (Read 837 times)
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Why did the post-layout simulation result incorrectly
Jan 24th, 2018, 4:05pm
I am working on the full digital implementation using Synopsys/Cadence tools.

The implementation steps include: (1) Synthesized by Design compiler -> (2) Simulated netlist by VCS -> (3) Place&Route by IC Compiler -> (4) Simulated ICC file by VCS -> (5) DRC/LVS/Antenna check by Calibre -> (6) Simulated spice file of LVS by nanosim -> (7) Extracted C and RC by starrc -> (8) Simulated C extracted file by nanosim -> (9) Simulated RC extracted file by nanosim.

Steps (1) to (8) delivered correct results (log files) and waveform. However, the simulation results in step (9) was incorrect.

Could you please give some solutions for this problem, e.g. what step should I check again etc.

Thank you very much.
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Andrew Beckett
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Re: Why did the post-layout simulation result incorrectly
Reply #1 - Jan 27th, 2018, 8:45am
Perhaps you should trace the signals in the simulation that was "incorrect" (you didn't say how it was incorrect) to determine what is going on. One possibility is that the delays caused by the parasitics are long enough that it alters the timing in the circuit leading to logic errors (e.g. due to setup and hold violations, or glitches - there are a number of different failure mechanisms).

Just repeating a step is unlikely to fix anything...


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