Andrew Beckett
Senior Fellow
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Life, don't talk to me about Life...
Posts: 1742
Bracknell, UK
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Perhaps you should trace the signals in the simulation that was "incorrect" (you didn't say how it was incorrect) to determine what is going on. One possibility is that the delays caused by the parasitics are long enough that it alters the timing in the circuit leading to logic errors (e.g. due to setup and hold violations, or glitches - there are a number of different failure mechanisms).
Just repeating a step is unlikely to fix anything...
Regards,
Andrew.
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