Thanks a lot Daniel. I will read the paper.

Yes, the circuit bench is just for switch noise. As you suggest, a small 1/16pF capacitor is added as parasitic comparator capacitance. The simulation shows the integrated noise on the same node is 256uV which is equal to be sqrt(kT/(1/16p)). it seems like all other capacitors except the parasitic cap have no effect on the output noise.

Considering the sampling noise is only sqrt(kT/(16p))=16uV. This is almost negligible compared with 256uV as calculated above. It seems it can be concluded the DAC noise is dominated by parasitic capacitance of the comparator(1/16p). To lower the DAC noise, one has to increase the parasitic cap of the comparator.

When it comes to noise budget of the DAC, it's more reasonable to consider the comparator parasitic capacitance than the overall sampling capacitors. Is this correct?

Additionally, do you happen to know how to calculate the sampling noise accurately and mathematically? Because during the sampling phase, taking the switch resistor into consideration, the sampling network is not a simple RC low pass filter structure. It's quite difficult to derive the sampling noise is kt/Ctot.

Regards,

-Mike

**DanielLam wrote on Mar 2**^{nd}, 2017, 10:24pm:Hi,

SAR ADCs have a few noise sources: kt/C from sampling, comparator noise, reference/switch noise. I am guessing you are seeing reference/switch noise. By the way, usually a comparator is connected to Vtop, and the comparator input capacitance will lowpass filter the noise (reducing the total noise from the dac array).

I suggest looking at this paper "A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques"

Just my 2 cents, let me know if I'm wrong.