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Design >> Mixed-Signal Design >> SAR ADC KT/C Noise
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Message started by Mikay on Mar 2^nd, 2017, 10:45am

Title: SAR ADC KT/C Noise
Post by Mikay on Mar 2^nd, 2017, 10:45am

When it comes to SAR ADC design. Everybody assumes the thermal noise introduced by the DAC bank is kt/C, wherein C is the total sum of DAC bank capacitors.

For a 5 bits accuracy, this will be

kt/(32C).

However, If we look at the figure as below, at higher frequency all of the capacitors are actually short and all the thermal noise in the switches will appear at the comparator input node vx. The noise will absolutely not be equal to kt/(32C).

A 5 bits test bench is made in the Spectre ADE, switched are replaced with resistors(10 ohm), unit cap is set set to be 0.5pF. noise simulation frequency range is from 1 to 100000T.

The result confirm the noise is not kt/(32*0.5pF). Integrated noise is actually hugely large, approximately 0.052v, which is large enough to deteriorate the ADC accuracy.

Anybody know where the discrepancy come from?

Title: Re: SAR ADC KT/C Noise
Post by Mikay on Mar 2^nd, 2017, 10:47am

The picture shows the test bench, the switches in the DAC bank are just replaced with small resistors.

Title: Re: SAR ADC KT/C Noise
Post by DanielLam on Mar 2^nd, 2017, 10:24pm

Hi,

SAR ADCs have a few noise sources: kt/C from sampling, comparator noise, reference/switch noise. I am guessing you are seeing reference/switch noise. By the way, usually a comparator is connected to Vtop, and the comparator input capacitance will lowpass filter the noise (reducing the total noise from the dac array).

I suggest looking at this paper "A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques"

Just my 2 cents, let me know if I'm wrong.

Title: Re: SAR ADC KT/C Noise
Post by Mikay on Mar 3^rd, 2017, 7:31am

Thanks a lot Daniel. I will read the paper.

Yes, the circuit bench is just for switch noise. As you suggest, a small 1/16pF capacitor is added as parasitic comparator capacitance. The simulation shows the integrated noise on the same node is 256uV which is equal to be sqrt(kT/(1/16p)). it seems like all other capacitors except the parasitic cap have no effect on the output noise.

Considering the sampling noise is only sqrt(kT/(16p))=16uV. This is almost negligible compared with 256uV as calculated above. It seems it can be concluded the DAC noise is dominated by parasitic capacitance of the comparator(1/16p). To lower the DAC noise, one has to increase the parasitic cap of the comparator.

When it comes to noise budget of the DAC, it's more reasonable to consider the comparator parasitic capacitance than the overall sampling capacitors. Is this correct?

Additionally, do you happen to know how to calculate the sampling noise accurately and mathematically? Because during the sampling phase, taking the switch resistor into consideration, the sampling network is not a simple RC low pass filter structure. It's quite difficult to derive the sampling noise is kt/Ctot.

Regards,
-Mike

DanielLam wrote on Mar 2^nd, 2017, 10:24pm:

Title: Re: SAR ADC KT/C Noise
Post by Mikay on Mar 4^th, 2017, 9:27am

Hi Daniel, Thanks for your recommended paper. Now I think I understand well the switch noise from DAC. Can you shed a light on how to calculate the sampling noise. Because there are switch connected to both top and bottom plate. It seem it's not trivial to calculate the total sampling noise. It's not a simple one order RC filter.

DanielLam wrote on Mar 2^nd, 2017, 10:24pm:

Title: Re: SAR ADC KT/C Noise
Post by DanielLam on Mar 7^th, 2017, 12:04am

When it comes to noise budget of the DAC, it's more reasonable to consider the comparator parasitic capacitance than the overall sampling capacitors. Is this correct?

It is whatever the top-plate parasitic to ground is. Comparator input, top plate metal routing, capacitor top plate.

Can you shed a light on how to calculate the sampling noise.
Sampled noise power is kT/C , if you want to input-refer it. You can multiply it by the attenuation factor.

Check out "A 2.8 GS/s 44.6 mW Time-Interleaved ADC
Achieving 50.9 dB SNDR and 3 dB Effective
Resolution Bandwidth of 1.5 GHz in 65 nm CMOS"

It's not a simple one order RC filter. Sure, but most people consider it one for simplicity. In practicality, I haven't ever experienced the sampling noise as the dominant noise source. The dominant factor is usually the comparator noise, and then perhaps the DAC noise.

Title: Re: SAR ADC KT/C Noise
Post by Mikay on Mar 8^th, 2017, 10:36am

Thanks! I think I understand well now.

Title: Re: SAR ADC KT/C Noise
Post by sutapanaki on May 8^th, 2017, 5:50pm

Hi Mikay,

I have also come across this topic and even have done some theoretical derivations on the noise at the input of the comparator during sampling and during bit conversions. If you don't take into account the ref switch resistances, then during sampling noise is kT/Cdac. However, if you also include those resistances, result should be expected to be different. Based on the derivations I did (also some simulations to confirm the result) noise comes to be kT/Cpar, where Cpar is the parasitic capacitance at the comparator input to ground. There are few things, though, that need to be said in this regard.
1. How does the comaparator BW affect the noise? For example if we consider noise from the CDAC not at the input of the comparator (i.e. at the preamplifier inputs) but rather at the latch inputs, then the BW of the preamplifier affects the result and depending on the ratio of that BW and the CDAC BW, result can get closer to kT/Cdac.
2. In my derivations and in your test bench as well, there are no parasitic capacitors between the ref voltage switches and the plates of the DAC capacitors connecting to those switches. I didn't use them since it complicates a lot the derivations. But I think they will affect the result. I know it's been few months since you posted this but if you're still curious you could include those parasitics and resimulate and see what the result is. I'll be interested to know.

Title: Re: SAR ADC KT/C Noise
Post by Frank_Heart on Nov 17^th, 2017, 10:27am

Usually I assume 4KTR noise on DAC resistor, and integrate it up to BW of CMP.

For CMP with a pre-amp, it is straight forwards to find out the BW.

While for high-speed SAR, usually I am using latch (like strong-arm latch) directly, which gives me uncertainty about BW.

I usually take 1/t_clkq as the BW for rough estimation.

I have opened another thread, and see if people have better idea to calculate BW of dynamic latch.

-Frank