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Oct 21st, 2021, 2:03pm
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How to simulate the "unlatched gain" of a dynamic comparator (Read 194 times)
wax and wane
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How to simulate the "unlatched gain" of a dynamic comparator
May 09th, 2021, 10:42pm
 
Hi everybody,

I have read the paper "Comparator Metastability Analysis" from this Forum and try to test the probability of comparators make a wrong disicion.

https://designers-guide.org/analysis/metastability.pdf

In this paper, there is a definition that Aul is the comparator unlatched gain. But how to simulate the "unlatched gain" of the dynamic comparator like strong arm and double-tailes ?

I'm confused about the definition and the simulation way about the "unlatched gain",can you give me some advise or the simulation guide?

It's the first time I use this Forum. Thanks a lot!
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Horror Vacui
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Re: How to simulate the "unlatched gain" of a dynamic comparator
Reply #1 - Jun 28th, 2021, 1:09am
 
Without consulting that paper (I've read it maybe 8 years ago...) I guess this is the analog gain when the dynamic latch is released from a reset state. Reset state here means when the gain stages are balanced to remove any voltage imbalance due to the previous decision. Therefore you should just measure the loop gain of the gain stage with an stb analysis.
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